DAC5670-SP_15 Datasheet, PDF (11/34 Pages) Texas Instruments – DAC5670-SP 14-Bit 2.4-GSPS Digital-to-Analog Converter (DAC)

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DAC5670-SP
SGLS386F – JANUARY 2009 – REVISED OCTOBER 2014
7.7 Digital Electrical Characteristics
T_C,MIN = –55°C to T_C,MAX = 125°C, typical values at 25°C, AVDD = 3 to 3.6 V, IoutFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾ MAX UNIT
CMOS INTERFACE (SLEEP, RESTART, INV_CLK, NORMAL, A_ONLY, A_ONLY_INV, A_ONLY_ZS)
I_IH
High-level input current
I_IL
Low-level input current
Input capacitance
0.2 10 μA
–10
–0.2
μA
2.5 ⁽²⁾
pF
DIFFERENTIAL DATA INTERFACE (DA_P[13:0], DA_N[13:0], DB_P[13:0], DB_N[13:0], DTCLK_P, DTCLK_N)
Z_T
Internal termination impedance
C_i
Input capacitance
80
100 125
Ω
2.6 ⁽²⁾
pF
(1) Typicals are characterization values at 25°C and AVDD = 3.3 V. These parameters are characterized, but not production tested.
(2) Specified by design.
7.8 Timing Requirements
MIN
TYP
MAX UNIT
DIFFERENTIAL DATA INTERFACE (DA_P[13:0], DA_N[13:0], DB_P[13:0], DB_N[13:0] EXTERNAL TIMING WITH DLL IN RESTART)
(See Figure 2)
t_setup
Data setup to DLYCLK⁽¹⁾
RESTART = 1, DLYCLK 20-pF load
See Figure 2
4.75
nS
t_hold
Data hold to DLYCLK ⁽¹⁾
RESTART = 1, DLYCLK 20-pF load
See Figure 2
–3.5
nS
DLL (See Figure 15)
NegD DLL min negative delay
RESTART = 0
150
ps
PosD DLL min positive delay
RESTART = 0
600
ps
t_valid
CLK/4 internal setup + hold
width
160
ps
Fdac
RESTART = 0
1
2.4 GHz
(1) Tested using SNR as pass/fail criteria.
DACLK_P/N
DACCLK/2 internal
toDAC5670
This internal DACCLK/2 is used to clock the input data DA and DB into theDAC5670
DLYCLK is DACCLK/4 delayed by the DAC5670 DLL to be used as the DDR clock for the data source digital chip
DLYCLK_P/N
DTCLK_P/N
DTCLK is a toggling bit, aligned with DA and DB data from chip, used by the DAC5670 DLL feedback path
DA_P/N[13:0]
DB_P/N[13:0]
internal data to
the DAC core in
NORMAL mode
a0
a1
a2
b0
b1
b2
a0
b0
7 DACCLKs
Pipeline Delay
Figure 1. DLL Input Loop Functional Timing
a3
b3
a1
b1
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