BQ26150 Datasheet, PDF (11/16 Pages) Texas Instruments – BATTERY PACK SECURITY AND AUTHENTICATION IC FOR PORTABLE APPLICATIONS (bqSECURE)

www.ti.com
bq26150
SLUS641A – JANUARY 2005 – REVISED JULY 2005
V_PROG
V_Pull-up
GND
t_RISE
t_PROG
Figure 7. OTP Programming Pulse
t_FALL
Table 2. OTP Programming Specifications
t_PON
t_RISE
t_PROG
t_FALL
PARAMETER
Write to pulse rise
Pulse rise time
Pulse high time
Pulse fall time
TEST CONDITIONS
No overshoot above 7.7 V
MIN
MAX UNIT
2
µs
1
10 µs
300
µs
1
10 µs
The nonvolatile memory can be written to more than once. However, the data already in the byte goes through a
logical bitwise OR with the new data. For example, if address 0x71 was programmed with data 0x55 initially and
a second program to address 0x71 with data 0xAA was performed, subsequent reads of address 0x71 would
return data 0xFF (0x55 OR 0xAA = 0xFF).
Communication With a 2^nd HDQ Device
The bq26150 has two communication pass through modes to allow communication to a second HDQ based
device from Texas Instruments. These modes allow the bq26150 to be put in an existing system utilizing a
bq2018, bq2019, bq262xx, or bq27xxx device. The pass through modes can be enabled by setting the CPASS or
OPASS bits in the control register.
The Continuous Pass Through (CPT) mode is enabled when the CPASS bit is set. While in this mode the
bq26150 passes all communication through to the 2^nd device on the bus. The CPT mode is cancelled when the
host transmits three consecutive breaks. Note that the 2^nd device on the bus may only see two of these three
breaks. The CPASS bit automatically clears after the third break is received.
The One Pass Through (OPT) mode is enabled when the OPASS bit is set. While in this mode, the bq26150
passes 16 valid HDQ bits. This allows the host to perform a single read or write to the 2nd HDQ device. The
OPT mode is cleared after the 16^th valid HDQ bit passes through the bq26150 or when 3 consecutive breaks are
received from the host. Note that the 2^nd HDQ device may only see two of these three breaks. The OPASS bit is
automatically cleared after the 16^th bit or the third break.
The OPT mode is useful for putting a 2^nd HDQ device to sleep. The OPASS bit can be set in the bq26150,
allowing the sleep command to be passed to the 2^nd HDQ device. After the 16^th bit is received from the host,
communication reverts to the bq26150. The HDQP line will not be disturbed and the 2^nd device enters sleep
mode as expected.
If the host writes both the CPASS and OPASS bits, the CPASS bit has priority and remains set after the first
pass through is completed. The OPASS bit is cleared.
Sending a Break During a Pass Through Read:
The bq26150 pass through mode is implemented in logic rather than connecting the HDQ/HDQP pads directly
through an analog transmission gate. This means the bq26150 cannot transmit the first break it receives to the
2^nd device while the data is being driven from the 2^nd device to the master. To transmit a break to the 2^nd device
while it is transmitting, the host is required to send 2 breaks. The first resets the bq26150 engine and prepares it
to transmit from the host to the 2^nd device. The second break actually reaches the 2^nd HDQ device.
Putting a bq262x0 to Sleep using Pass Through:
11