SM320F2810-EP_11 Datasheet, PDF (109/158 Pages) Texas Instruments – Digital Signal Processors

Electrical Specifications
6.17 Event Manager Interface
6.17.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
Table 6−13. PWM Switching Characteristics^†‡
PARAMETER
TEST CONDITIONS
t_w(PWM)§
Pulse duration, PWMx output high/low
t_d(PWM)XCO
Delay time, XCLKOUT high to PWMx output switching
XCLKOUT = SYSCLKOUT/4
† _{See the GPIO output timing for fall/rise times for PWM pins.}
‡ _{PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).}
§ _{PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.}
Table 6−14. Timer and Capture Unit Timing Requirements^¶#
MIN MAX UNIT
25
ns
10 ns
MIN
MAX UNIT
t_w(TDIR)
t_w(CAP)
Pulse duration, TDIRx low/high
Pulse duration, CAPx input low/high
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
2 * t_c(SCO)
1 * t_c(SCO) + IQT^||
2 * t_c(SCO)
1 * t_c(SCO) + IQT^||
cycles
cycles
t_w(TCLKINL)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
40
60 %
t_w(TCLKINH)
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
40
60 %
t_c(TCLKIN)
Cycle time, TCLKINx
4 * t_c(HCO)
ns
¶ _{The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling period is}
2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the qualification sampling
period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples will be taken over five sampling
windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles.
However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition.
# _{Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]}
|| _{Input Qualification Time (IQT) = [5 x QUALPRD x 2] * tc(SCO)}
XCLKOUT^†
t_d(PWM)XCO
PWMx
† _{XCLKOUT = SYSCLKOUT}
t_w(PWM)
Figure 6−16. PWM Output Timing
XCLKOUT^†
TDIRx
† _{XCLKOUT = SYSCLKOUT}
t_w(TDIR)
Figure 6−17. TDIRx Timing
March 2004 − Revised April 2010
SGUS051B 109