TAS1020BPFBR Datasheet, PDF (105/118 Pages) Texas Instruments – USB Streaming Controller

TAS1020B
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SLES025B – JANUARY 2002 – REVISED MAY 2011
6.5.4.6 Codec Port Interface Address Register (CPTADR - Address FFDBh)
The codec port interface address register contains the read/write control bit and address bits used for
secondary communication between the TAS1020B MCU and the codec device. For write transactions to
the codec, the 8-bit value in this register is sent to the codec in the designated time slot and appropriate
bit locations. Note that for the different modes of operation, the number of address bits and the bit location
of the read/write bit is different. For example, the AC ’97 modes require 7 address bits and the bit location
of the read/write bit to be the most significant bit. The AIC mode only requires 4 address bits and the bit
location of the read/write bit to be bit 13 of the 16-bits in the time slot. The MCU must load the read/write
and address bits to the correct bit locations within this register for the different modes of operation. Shown
below are the read/write control bit and address bits for the AC ’97 mode of operation.
Bit
7
6
5
4
3
2
1
0
Mnemonic
R/W
A6
A5
A4
A3
A2
A1
A0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
BIT MNEMONIC
NAME
7
R/W
Command/status
read/write control
6:0
A(6:0)
Command/status
address
DESCRIPTION
The command/status read/write control bit value is set by the MCU to program the
type of secondary communication transaction to be done. This bit must be set to a 1
by the MCU for a read transaction and cleared to a 0 by the MCU for a write
transaction.
The command/status address value is set by the MCU to program the codec device
control/status register address to be accessed during the read or write transaction.
The command/status address value is updated by hardware with the control/status
register address value received from the codec device for read transactions.
6.5.4.7 Codec Port Interface Data Register (Low Byte) (CPTDATL - Address FFDAh)
The codec port interface data register (low byte) contains the least significant byte of the 16-bit command
or status data value used for secondary communication between the TAS1020B MCU and the codec
device. Note that for general-purpose mode or AIC mode only an 8-bit data value is used for secondary
communication.
Bit
7
6
5
4
3
2
1
0
Mnemonic
D7
D6
D5
D4
D3
D2
D1
D0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
BIT MNEMONIC
NAME
DESCRIPTION
The command/status data value is set by the MCU with the command data to be
7:0
D(7:0)
Command/status data
transmitted to the codec device for write transactions. The command/status data value
is updated by hardware with the status data received from the codec device for read
transactions.
6.5.4.8 Codec Port Interface Data Register (High Byte) (CPTDATH - Address FFD9h)
The codec port interface data register (high byte) contains the most significant byte of the 16-bit command
or status data value used for secondary communication between the TAS1020B MCU and the codec
device. This register is not used for general-purpose mode or AIC mode since these modes only support
an 8-bit data value for secondary communication.
Bit
7
6
5
4
3
2
1
0
Mnemonic
D15
D14
D13
D12
D11
D10
D9
D8
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
BIT MNEMONIC
NAME
DESCRIPTION
The command/status data value is set by the MCU with the command data to be
7:0
D(15:8)
Command/status data
transmitted to the codec device for write transactions. The command/status data value
is updated by hardware with the status data received from the codec device for read
transactions.
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MCU Memory and Memory-Mapped Registers 105
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