TMS320C6410 Datasheet, PDF (104/140 Pages) Texas Instruments – Fixed-Point Digital Signal Processors

Synchronous DRAM Timing
7.4 Synchronous DRAM Timing
Table 7−12. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 7−12)
NO.
6
t_{su(EDV-EKO1H)}
7
t_h(EKO1H-EDV)
Setup time, read AEDx valid before AECLKOUTx high
Hold time, read AEDx valid after AECLKOUTx high
−400
−500
MIN MAX
2.1
2.5
UNIT
ns
ns
Table 7−13. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module (see Figure 7−12−Figure 7−19)
NO.
1
t_d(EKO1H-CEV)
2
t_d(EKO1H-BEV)
3
t_{d(EKO1H-BEIV)}
4
t_d(EKO1H-EAV)
5
t_{d(EKO1H-EAIV)}
8
t_{d(EKO1H-CASV)}
9
t_d(EKO1H-EDV)
10 t_{d(EKO1H-EDIV)}
11 t_d(EKO1H-WEV)
12 t_d(EKO1H-RAS)
13 t_{d(EKO1H-ACKEV)}
14 t_{d(EKO1H-PDTV)}
PARAMETER
Delay time, AECLKOUTx high to ACEx valid
Delay time, AECLKOUTx high to ABEx valid
Delay time, AECLKOUTx high to ABEx invalid
Delay time, AECLKOUTx high to AEAx valid
Delay time, AECLKOUTx high to AEAx invalid
Delay time, AECLKOUTx high to ASDCAS valid
Delay time, AECLKOUTx high to AEDx valid
Delay time, AECLKOUTx high to AEDx invalid
Delay time, AECLKOUTx high to ASDWE valid
Delay time, AECLKOUTx high to ASDRAS valid
Delay time, AECLKOUTx high to ASDCKE valid
Delay time, AECLKOUTx high to PDT valid
−400
−500
MIN MAX
1.3 6.4
6.4
1.3
6.4
1.3
1.3 6.4
6.4
1.3
1.3 6.4
1.3 6.4
1.3 6.4
1.3 6.4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
104 SPRS247E
April 2004 − Revised May 2005