TMS320C6411 Datasheet, PDF (102/119 Pages) Texas Instruments – FIXED POINT DIGITAL SIGNAL PROCESSOR

TMS320C6411
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
timing requirements for McBSP^† (see Figure 51)
NO.
2 tc(CKRX)
3 tw(CKRX)
5 tsu(FRH-CKRL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
−300
MIN
4P or 6.67द
0.5tc(CKRX) − 1#
9
1.3
MAX
UNIT
ns
ns
ns
CLKR int
6
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR ext
3
ns
CLKR int
8
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR ext
0.9
ns
CLKR int
3
8 th(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR ext
3.1
ns
CLKX int
9
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
CLKX ext
1.3
ns
CLKX int
6
11 th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing}
requirements.
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.}
¶ _{Use whichever value is greater.}
# _{This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the resonable range of 40/60 duty cycle.}
102
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