TPA5050 Datasheet, PDF (10/17 Pages) Texas Instruments – STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL

TPA5050
SLOS492A – MAY 2006 – REVISED MAY 2006
SERIAL CONTROL INTERFACE REGISTER SUMMARY
REGISTER
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Table 2. Serial Control Register Summary
REGISTER NAME
Control Register
Right Delay Upper (5 bits)
Right Delay Lower (8 bits)
Left Delay Upper (5 bits)
Left Delay Lower (8 bits)
Frame Delay
RJ Packet Length
Complete Update
NO. OF
BYTES
1
1
1
1
1
1
1
1
CONTENTS
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INITIALIZATION
VALUE
00
00
00
00
00
00
00
00
CONTROL REGISTER (0x01)
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I²S,
Right-Justified, or Left-Justified.
D7 D6 D5 D4 D3
0
0
X
X
X
0
1
X
X
X
1
0
X
X
X
1
1
X
X
X
–
–
X
X
X
–
–
X
X
X
–
–
X
X
X
–
–
X
X
X
(1) Default values are in bold.
Table 3. Control Registers (0x01)⁽¹⁾
D2 D1 D0
FUNCTION
X
–
– Left and Right channel are active.
X
–
– Left channel is MUTED.
X
–
– Right channel is MUTED.
X
–
– Left and Right channel are MUTED.
X
0
0 I²S data format
X
0
1 Right-justified data format (see PACKET LENGTH register 0x07)
X
1
0 Left-justified data format
X
1
1 Bypass mode – data is passed straight through without delay.
AUDIO DELAY REGISTERS (0x02–0x05)
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper and
lower registers as specified in Table 1. A multiple byte transfer should be performed starting with the control
register and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay.
The decimal value of D0–D13 equals the number of samples to delay. The maximum number of delayed
samples is 8191 for the TPA5050. This equates to 170.65 ms [8191 × (1/fs)] at 48 kHz.
D13
D12
D11–D2
0
0
0
0
0
0
1
1
1
(1) Default values are in bold.
Table 4. Audio Delay Registers (0x02–0x05)⁽¹⁾
D1
D0
FUNCTION
0
0 Left and Right audio is passed to output with no delay.
0
1 Left and Right audio is delayed by 1 sample (1/fs = delay time)
1
1 Left and Right audio is delayed by 8191 samples (8191/fs = delay time)
FRAME DELAY REGISTERS (0x06)
This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to 1,
the audio delay registers (0x01–0x04) are bypassed and the Frame Delay Register is used to set the delay
based on the frame rate (D6), audio sample rate (D5–D3), and number of frames to delay (D2–D0).
The total audio delay time is calculated by the following formula:
Audio Delay (in samples) = int [# Delay Frames × (1/Frame Rate) × Audio Sample Rate]
10
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