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TMS320UC5402 Datasheet, PDF (10/63 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMS320UC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS096A – APRIL 1999 – REVISED DECEMBER 1999
memory
The ’UC5402 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
on-chip ROM with bootloader
The ’UC5402 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM
of the ’UC5402 programmed with contents unique to any particular application. A security option is available
to protect a custom ROM. This security option is described in the TMS320C54x DSP CPU and Peripherals
Reference Set, Volume 1 (literature number SPRU131). Note that only the ROM security option, and not the
ROM/RAM option, is available on the ’UC5402 .
A bootloader is available in the standard ’UC5402 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin
is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location
contains a branch instruction to the start of the bootloader program. The standard ’UC5402 bootloader provides
different ways to download the code to accomodate various system requirements:
D Parallel from 8-bit or 16-bit-wide EPROM
D Parallel from I/O space 8-bit or 16-bit mode
D Serial boot from serial ports 8-bit or 16-bit mode
D Host-port interface boot
The standard on-chip ROM layout is shown in Table 1.
Table 1. Standard On-Chip ROM Layout†
ADDRESS RANGE
F000h – F7FFh Reserved
DESCRIPTION
F800h – FBFFh Bootloader
FC00h – FCFFh µ-law expansion table
FD00h – FDFFh A-law expansion table
FE00h – FEFFh Sine look-up table
FF00h – FF7Fh Reserved
FF80h – FFFFh Interrupt vector table
† In the ’UC5402 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
on-chip RAM
The ’UC5402 device contains 16K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed
of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and
a write in one cycle. The DARAM is located in the address range 0080h–3FFFh in data space, and can be
mapped into program/data space by setting the OVLY bit to 1.
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