TFP401A-Q1 Datasheet, PDF (10/23 Pages) Texas Instruments – TI PanelBus DIGITAL RECEIVER

TFP401A-Q1
SLDS190 – NOVEMBER 2012
PARAMETER MEASUREMENT INFORMATION (continued)
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PD
QE[23:0], QO[23:0],
ODCK, DE, CTL[3:1],
HSYNC, VSYNC, SCDT
V_IL
t_pd(PDL)
Figure 7. Delay From PD Low to Hi-Z Outputs
N
N
PDO
QE[23:0], QO[23:0],
ODCK, DE, CTL[3:2],
HSYNC, VSYNC
V_IL
t_pd(PDOL)
Figure 8. Delay From PDO Low to Hi-Z Outputs
N
N
V_IH
PD
DFO, ST, PIXS, STAG,
Rx[2:0]+, Rx[2:0]–,
OCK_INV
t_p(PDH-V)
Figure 9. Delay From PD Low to High
Before Inputs Are Active
N
N
t_{wL(PDL_MIN)}
PD
V_IL
Figure 10. Minimum Time PD Low
N
N
TX2 50%
TX1
t_ccs
TX0 ^50%
Figure 11. Analog Input Channel-to-Channel Skew
N
N
t_t(HSC)
DE
t_t(FSC)
SCDT
Figure 12. Time Between DE Transitions to SCDT Low and SCDT High
N
N
t_DEL
t_DEH
DE
Figure 13. Minimum DE Low and Maximum DE High
10
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