TAS5630B Datasheet, PDF (10/36 Pages) Texas Instruments – 300-W STEREO / 400-W MONO PurePath™ HD ANALOG-INPUT POWER STAGE

TAS5630B
SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012
www.ti.com
AUDIO SPECIFICATION (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, R_L = 3 Ω, f_S = 400 kHz, R_OC = 22 kΩ, T_C = 75°C; output filter: L_DEM = 7 μH, C_DEM = 1.5 μF,
MODE = 101-10, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
P_O
Power output per channel
THD+N Total harmonic distortion + noise
R_L = 3 Ω, 10% THD+N, clipped output signal
R_L = 4 Ω, 10% THD+N, clipped output signal
R_L = 3 Ω, 1% THD+N, unclipped output signal
R_L = 4 Ω, 1% THD+N, unclipped output signal
1W
400
300
W
310
230
0.05%
V_n
SNR
Output integrated noise
Signal to noise ratio⁽¹⁾
A-weighted
A-weighted
260
μV
100
dB
DNR
P_idle
Dynamic range
A-weighted
Power dissipation due to idle losses (IPVDD_X) P_O = 0, four channels switching⁽²⁾
100
dB
2.7
W
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, T_C (Case temperature) = 75°C, f_S = 400 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference
node, VREG
VDD = 12 V
3 3.3 3.6 V
VI_CM
Analog comparator reference node, VI_CM
1.75
2 2.15 V
I_VDD
VDD supply current
Operating, 50% duty cycle
Idle, reset mode
22.5
mA
22.5
I_{GVDD_X}
50% duty cycle
GVDD_x gate-supply current per half-bridge
Reset mode
12.5
mA
1.5
I_{PVDD_X}
Half-bridge supply current
50% duty cycle with recommended output
filter
13.3
mA
Reset mode, No switching
870
μA
ANALOG INPUTS
R_IN
Input resistance
READY = HIGH
V_IN
Maximum input voltage with symmetrical
output swing
33
kΩ
5
V_PP
I_IN
G
OSCILLATOR
Maximum input current
Voltage gain (V_OUT/V_IN)
342
μA
23
dB
Nominal, master mode
3.85
4 4.15
f_{OSC_IO+}
AM1, master mode
AM2, master mode
F_PWM × 10
3.15 3.33 3.5 MHz
2.6
3 3.35
V_IH
High level input voltage
V_IL
Low level input voltage
OUTPUT-STAGE MOSFETs
1.86
V
1.45 V
R_DS(on)
Drain-to-source resistance, low side (LS)
Drain-to-source resistance, high side (HS)
T_J = 25°C, excludes metallization
resistance, GVDD = 12 V
60 100 mΩ
60 100 mΩ
10
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