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SN74AVCAH164245_02 Datasheet, PDF (10/11 Pages) Texas Instruments – 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SN74AVCAH164245
16-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES396 – JULY 2002
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
RL
RL
2 × VCCO
S1
Open
GND
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 × VCCO
GND
LOAD CIRCUIT
VCCO
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
CL
15 pF
30 pF
30 pF
30 pF
RL
2 kΩ
1 kΩ
500 Ω
500 Ω
VTP
0.1 V
0.15 V
0.15 V
0.3 V
Input
tw
VCCI/2
VCCI/2
VOLTAGE WAVEFORMS
PULSE DURATION
VCCI
0V
Output
Control
(low-level
enabling)
VCCB/2
VCCB/2
VCCB
0V
Input
tPLH
Output
tPZL
tPLZ
VCCI/2
VCCO/2
VCCI/2
VCCI
Output
Waveform 1
0 V S1 at 2 × VCCO
(see Note B)
tPHL
VOH
VCCO/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
tPZH
VCCO/2
VCCO/2
VCCO
VOL + VTP
VOL
tPHZ
VOH
VOH – VTP
0V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
v Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns,
dv/dt ≥1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 2. Load Circuit and Voltage Waveforms
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