SN54ABT8652 Datasheet, PDF (10/25 Pages) Texas Instruments – SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996
data register description
boundary-scan register
The boundary-scan register (BSR) is 38 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input and two BSCs for each normal-function I/O (one for input data and one for output data).
The BSR is used to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or
externally to the device output terminals, and/or to capture data that appears internally at the outputs of the
normal on-chip logic and/or externally at the device input terminals.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, the value of each BSC is reset to logic 0 except BSC 36, which is reset to logic 1.
The BSR order of scan is from TDI through bits 37–0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
BSR BIT
NUMBER
37
36
35
34
33
32
––
––
DEVICE
SIGNAL
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
––
––
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
31
30
29
28
27
26
25
24
DEVICE
SIGNAL
A8-I
A7-I
A6-I
A5-I
A4-I
A3-I
A2-I
A1-I
BSR BIT
NUMBER
23
22
21
20
19
18
17
16
DEVICE
SIGNAL
A8-O
A7-O
A6-O
A5-O
A4-O
A3-O
A2-O
A1-O
BSR BIT
NUMBER
15
14
13
12
11
10
9
8
DEVICE
SIGNAL
B8-I
B7-I
B6-I
B5-I
B4-I
B3-I
B2-I
B1-I
BSR BIT
NUMBER
7
6
5
4
3
2
1
0
DEVICE
SIGNAL
B8-O
B7-O
B6-O
B5-O
B4-O
B3-O
B2-O
B1-O
boundary-control register
The boundary-control register (BCR) is 11 bits long. The BCR is used in the context of the RUNT instruction to
implement additional test operations not included in the basic SCOPE™ instruction set. Such operations include
PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that are
decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 00000000010, which selects the PSA test operation with no input masking.
The BCR order of scan is from TDI through bits 10–0 to TDO. Table 2 shows the BCR bits and their associated
test control signals.
Table 2. Boundary-Control Register Configuration
BCR BIT
NUMBER
10
9
8
7
TEST
CONTROL
SIGNAL
MASK8
MASK7
MASK6
MASK5
BCR BIT
NUMBER
6
5
4
3
TEST
CONTROL
SIGNAL
MASK4
MASK3
MASK2
MASK1
BCR BIT
NUMBER
2
1
0

TEST
CONTROL
SIGNAL
OPCODE2
OPCODE1
OPCODE0

10
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