PCI1131 Datasheet, PDF (10/26 Pages) Texas Instruments – PCI-TO-CARDBUS CONTROLLER UNIT

PCI1131
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
Terminal Functions (Continued)
16-bit PC Card interface control signals (slots A and B)
TERMINAL
NUMBER
NAME
SLOT SLOT
A† B‡
I/O
TYPE
FUNCTION
BVD1
(STSCHG/RI)
138 72
Battery voltage detect 1. Generated by 16-bit memory PC Cards that include batteries. BVD1
is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both
BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high,
the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer
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serviceable and the data in the memory PC Card is lost.
Status change. STSCHG is used to alert the system to a change in the READY, write protect,
or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate ring detection.
BVD2(SPKR) 137 71
Battery voltage detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2
is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both
BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the
battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer
serviceable and the data in the memory PC Card is lost.
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Speaker. SPKR is an optional binary audio signal available only when the card and socket have
been configured for the 16-bit I/O interface. The audio signals from cards A and B can be
combined by the PCI1131 and output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, the PC Card asserts BVD2 to request a DMA operation.
CD1
CD2
82
16
140 74
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PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on
the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low.
CE1
CE2
94
97
28
30
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address
O bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address
bytes.
INPACK
127 61
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle
at the current address.
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DMA request. INPACK can be used as the DMA request signal during DMA operations to a
16-bit PC Card that supports DMA. If used, the PC Card asserts INPACK to indicate a request
for a DMA operation.
IORD
I/O read. IORD is asserted by the PCI1131 to enable 16-bit I/O PC Card data output during host
I/O read cycles.
99
33
O _{DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card}
that supports DMA. The PCI1131 asserts IORD during DMA transfers from the PC Card to host
memory.
IOWR
101 35
I/O write. IOWR is driven low by the PCI1131 to strobe write data into 16-bit I/O PC Cards during
host I/O write cycles.
O _{DMA read. IOWR is used as the DMA read strobe during DMA operations to a 16-bit PC Card}
that supports DMA. The PCI1131 asserts IOWR during DMA transfers from host memory to the
PC Card.
Output enable. OE is driven low by the PCI1131 to enable 16-bit memory PC Card data output
during host memory read cycles.
OE
98
32
O
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit
PC Card that supports DMA. The PCI1131 asserts OE to indicate TC for a DMA write operation.
† _{Terminal name is preceded with A_. For example, the full name for terminal 138 is A_BVD1.}
‡ _{Terminal name is preceded with B_. For example, the full name for terminal 72 is B_BVD1.}
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