OPA349NA Datasheet, PDF (10/23 Pages) Texas Instruments – 1A, Rail-to-Rail I/O CMOS OPERATIONAL AMPLIFIERS

DESIGN OPTIMIZATION WITH RAIL-TO-RAIL INPUT OP AMPS
In most applications, operation is within the range of only one
differential pair. However, some applications can subject the
amplifier to a common-mode signal in the transition region.
Under this condition, the inherent mismatch between the two
differential pairs may lead to degradation of the CMRR and
THD. The unity-gain buffer configuration is the most problem-
atic—it will traverse through the transition region if a sufficiently
wide input swing is required. A design option would be to
configure the op amp as a unity-gain inverter as shown below
and hold the noninverting input at a set common-mode voltage
outside the transition region. This can be accomplished with a
voltage divider from the supply. The voltage divider should be
designed such that the biasing point for the noninverting input
is outside the transition region.
R
R
V_OUT
V_IN
V_CM
FIGURE 3. Design Optimization.
COMMON-MODE REJECTION
The CMRR for the OPA349 is specified in two ways so the best
match for a given application may be used. First, the CMRR of
the device in the common-mode range below the transition
region (V_CM < (V+) – 1.5V) is given. This specification is the
best indicator of the capability of the device when the applica-
tion requires use of one of the differential input pairs. Second,
the CMRR at V_S = 5V over the entire common-mode range is
specified.
OUTPUT DRIVEN TO V– RAIL
Loads that connect to single-supply ground (or the V– supply
pin) can cause the OPA349 or OPA2349 to oscillate if the
output voltage is driven into the negative rail (as shown in
Figure 4a). Similarly, loads that can cause current to flow out
of the output pin when the output voltage is near V– can
cause oscillations. The op amp will recover to normal opera-
tion a few microseconds after the output is driven positively
out of the rail.
Some op amp applications can produce this condition even
without a load connected to V–. The integrator in Figure 4b
shows an example of this effect. Assume that the output
ramps negatively, and saturates near 0V. Any negative-
going step at V_IN will produce a positive output current pulse
through R₁ and C₁. This may incite the oscillation. Diode D₁
prevents the input step from pulling output current when the
output is saturated at the rail, thus preventing the oscillation.
a)
V+
OPA349
V_O
V_IN
R_L
0V
FIGURE 4. Output Driven to Negative Rail.
b)
R₁
1MΩ
V+
C₁
1nF
V_IN
2V
D1
0V
1N4148
OPA349
0V
(No Load)
1V
10
OPA349, 2349
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