LM3880MF-1AENOPB Datasheet, PDF (10/22 Pages) Texas Instruments – LM3880/LM3880Q-1 Power Sequencer

LM3880, LM3880Q-1
SNVS451I – AUGUST 2006 – REVISED MARCH 2013
www.ti.com
EN
FLAG1
t_d1
Figure 14. EN Glitch
If the enable signal remains high for the entire power-up sequence, then the part will operate as shown in the
standard timing diagrams. However, if the enable signal is de-asserted before the power-up sequence is
completed the part will enter a controlled shutdown. This allows the system to walk through a controlled power
cycling, preventing any latch conditions from occuring. This state only occurs if the enable pin is de-asserted
after the completion of timer 1, but before the entire power-up sequence is completed.
When this event occurs, the falling edge of enable pin resets the current timer and will allow the remaining
power-up cycle to complete before beginning the power down sequence. The power down sequence starts
approximately 120ms after the final power-up flag. This allows output voltages in the system to stabilize before
everything is shutdown. An example of this operation can be seen below:
EN
FLAG1
FLAG2
FLAG3
t_d1
t_d2
t_d3
120 ms
t_d4
t_d5
t_d6
Figure 15. Incomplete Sequence
All the internal timers are generated by a master clock that has an extremely low tempco. This allows for tight
accuracy across temperature and a consistent ratio between the individual timers. There is a slight additional
delay of approximately 400 µs to timers 1 and 4 which is a result of the EPROM refresh. This refresh time is in
addition to the programmed delay time and will be almost insignificant to all but the shortest of timer delays.
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