CDCE913_10 Datasheet, PDF (10/25 Pages) Texas Instruments – Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs

CDCE913
CDCEL913
SCAS849E – JUNE 2007 – REVISED MARCH 2010
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S1/SDA and S2/SCL pins of the CDCE913/CDCEL913 are dual function pins. In default configuration they are
defined as SDA/SCL for the serial programming interface. They can be programmed as control-pins (S1/S2) by
setting the appropriate bits in the EEPROM. Note that the changes to the Control Register (Bit [6] of Byte 02h)
have no effect until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if V_DDOUT is
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi use pin; it is a control pin only.
DEFAULT DEVICE CONFIGURATION
The internal EEPROM of CDCE913/CDCEL913 is pre-configured with a factory default configuration as shown in
Figure 6 (The input frequency is passed through the output as a default).This allows the device to operate in
default mode without the extra production step of programming it. The default setting appears after power is
supplied or after power-down/up sequence until it is reprogrammed by the user to a different application
configuration. A new register setting is programmed via the serial SDA/SCL Interface.
V_DD
GND
V_DDOUT
Input Clock
Xin
Pdiv1 =1
LV
CMOS
Y1 = 27 MHz
27 MHz
Crystal
Xout
1 = Output Enabled
0 = Output 3-State
Programming Bus
S0
SDA
SCL
X-tal
EEPROM
Programming
and
SDA/SCL
Register
PLL 1
power down
PLL Bypass
Pdiv2 = 1
Pdiv3 = 1
LV
CMOS
LV
CMOS
Y2 = 27 MHz
Y3 = 27 MHz
Figure 6. Default Configuration
Table 4 shows the factory default setting for the Control Terminal Register. Note that even though 8 different
register settings are possible, in default configuration, only the first two settings (0 and 1) can be selected with
S0, as S1 and S2 are configured as programming pins in default mode.
Table 4. Factory Default Setting for Control Terminal Register⁽¹⁾
External Control Pins
S2
S1
S0
SCL (I2C) SDA (I2C)
0
SCL (I2C) SDA (I2C)
1
Y1
Output Selection
Y1
3-state
enabled
Frequency Selection
FS1
f_{VCO1_0}
f_{VCO1_0}
PLL1 Settings
SSC Selection
SSC1
off
off
Output Selection
Y2Y3
3-state
enabled
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1=0 and S2=0. S0, however, is a control-pin which in the default mode
switches all outputs ON or OFF (as previously predefined).
SDA/SCL SERIAL INTERFACE
The CDCE913/CDCEL913 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the
popular SMBus or I2C specification. It operates in the standard-mode transfer (up to 100kbit/s) and fast-mode
transfer (up to 400kbit/s) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDCE913/CDCEL913 are dual function pins. In the default configuration
they are used as SDA/SCL serial programming interface. They can be re-programmed as general purpose
control pins, S1 and S2, by changing the corresponding EEPROM setting, Byte 02h, Bit [6].
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