CD54HC192_07 Datasheet, PDF (10/20 Pages) Texas Instruments – High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters

Test Circuits and Waveforms (Continued)
Pn
t_SU(H)
PL
t_H
Q=p
Q_n
V_S
t_SU(L)
V_S
t_H
INPUT LEVEL
INPUT LEVEL
V_S
Q=p
FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL)
DATA INPUT
UP CLOCK
DOWN CLOCK
ASYNCHRONOUS,
PARALLEL LOAD
RESET
P0 P1 P2 P3
CPU
TCU
CPD
TCD
PL
MR
Q₀ Q₁ Q₂ Q₃
P0 P1 P2 P3
CPU
TCU
CPD
TCD
PL
MR
Q₀ Q₁ Q₂ Q₃
BORROW
CARRY
OUTPUT
FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD
0
1
2
3
4
0
1
2
3
4
15
5
15
5
14
6
14
6
13
7
13
7
12
11
10
9
8
COUNT UP
12
11
10
9
8
COUNT DOWN
NOTE: Illegal states in BCD counters corrected in one count.
NOTE: Illegal states in BCD counters corrected in one or two counts.
FIGURE 9. ’HC192, ’HCT193 STATE DIAGRAMS
10