ADS901EG4 Datasheet, PDF (10/13 Pages) Texas Instruments – ANALOG-TO-DIGITAL CONVERTER

LOW-COST REFERENCE SOLUTION
The easiest way to achieve the required reference voltages is
to place the reference ladder of the ADS901 between the
supply rails, as shown in Figure 5. Two additional resistors
(R_T, R_B) are necessary to set the correct current through the
ladder. However depending on the desired full-scale swing
and supply voltage different resistor values might be se-
lected.
The trade-offs, when selecting this reference circuit, are
variations in the reference voltages due to component toler-
ances and power supply variations. In any case, it is recom-
mended to bypass the reference ladder with at least 0.1µF
ceramic capacitors, as shown in Figure 5. The capacitors
serve a dual purpose. They will bypass most of the high
frequency transient noise which results from feedthrough of
the clock and switching noise from the T/H stages. Sec-
ondly, they serve as a charge reservoir to supply instanta-
neous current to internal nodes.
SINGLE-ENDED INPUT
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
+FS (IN = +2V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +1.5V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1V)
1111111111
1111111111
1111111110
1110000000
1100000000
1010000000
1000000001
1000000000
0111111111
0110000000
0100000000
0010000000
0000000001
0000000000
TABLE I. Coding Table for the ADS901.
PRECISE REFERENCE SOLUTION
For those applications requiring a higher level of dc accu-
racy and drift, a reference circuit with a precision reference
element might be used (see Figure 6). A stable +1.2V
reference voltage is established by a two terminal bandgap
reference diode, the REF1004-1.2. Using a general-purpose
single-supply dual operational amplifier (A1), like an
OPA2237, OPA2234 or OPA2343, the two required refer-
ence voltages for the ADS901 can be generated by setting
each op amp to the appropriate gain; for example: set REFT
to +2V and REFB to +1V.
CLOCK INPUT
The clock input of the ADS901 is designed to accommodate
either +5V or +3V CMOS logic levels. To drive the clock
input with a minimum amount of duty cycle variation and
support maximum sampling rates (20Msps), high speed or
advanced CMOS logic should be used (HC/HCT, AC/ACT).
When digitizing at high sampling rates, a 50% duty cycle
clock with fast rise and fall times (2ns or less) are recom-
mended to meet the rated performance specifications. How-
ever, the ADS901 performance is tolerant to duty cycle
variations of as much as ±10% without degradation. For
applications operating with input frequencies up to Nyquist
or undersampling applications, special consideration must
be made to provide a clock with very low jitter. Clock jitter
leads to aperture jitter (t_A) which can be the ultimate limita-
tion to achieving good SNR performance. Equation (5)
shows the relationship between aperture jitter, input fre-
quency and the signal-to-noise ratio:
SNR = 20log₁₀ [1/(2 π f_IN t_A)]
(5)
For example, with a 10MHz full-scale input signal and an
aperture jitter of t_A = 20ps, the SNR is clock jitter limited to
58dB.
+3V
10µF
0.1µF
0.1µF
V_IN
1kΩ
+V_S
IN
ADS901
0.1µF ^CM
R_T
4kΩ
+2V
REFT
1kΩ
LpBy
1kΩ
0.1µF
0.1µF
1kΩ
LnBy
1kΩ
REFB
0.1µF
+1V
0.1µF
R_B
4kΩ
FIGURE 5. Low Cost Solution to Supply External Reference Voltages and Recommended Reference Bypassing.
10
ADS901
SBAS054A