ADS7882 Datasheet, PDF (10/29 Pages) Texas Instruments – 12-BIT, 3-MSPS LOW POWER SAR ANALOG-TO-DIGITAL CONVERTER

ADS7882
SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
CONVST
BUSY
CS
BYTE
D11−D0
Conversion No N
t_d2
t_d1 + t_(acq)
Data For Conv. N−1
t_d7
D11−4 & D3−0
D3−0
t_d8
Data For Conv. N
Figure 6. Read Control Via CS and RD Tied to BDGND
t₂
t_d10
DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION
Figure 7 and Figure 8 illustrate device operation in back-to-back conversion mode. It is possible to operate the
device at any throughput in this mode, but this is the only mode in which the device can be operated at
throughputs exceeding 2.83 MSPS (1/t_(acq) min + t_(conv) max + t_d11 max)).
A conversion starts on the CONVST falling edge. The BUSY output goes high after a delay (t_d2). Note that care
must be taken not to abort the conversion (see Figure 4) apart from timing restrictions shown in Figure 7 and
Figure 8. The conversion ends within the conversion time, t_(conv), after the CONVST falling edge. The new
acquisition can be immediately started without waiting for the BUSY signal to go low. This can be ensured with a
CONVST high pulse width that is more than or equal to (t₀ – t_(conv) + 10 nsec) which is t_w4 for a 3-MHz operation.
Sample N
CONVST
BUSY
D11−D0
t_w4
t_(acq)
t_w5
Conversion N
t_d12
t_(conv) + t_d11
Data For Conversion N−1
(Data Read without Latency)
t₀ = 333 ns for 3 MSPS Operation
Figure 7. Back-To-Back Operation With CS and RD Low
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