VSP8133 Datasheet, PDF (1/29 Pages) Texas Instruments – CCD Analog Front-End with Timing Generator for Digital Cameras

VSP8133
www.ti.com
SBES020A – JUNE 2011 – REVISED MAY 2013
CCD Analog Front-End with Timing Generator for Digital Cameras
Check for Samples: VSP8133
FEATURES
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•23 CCD Signal Processing:
– Correlated Double Sampling (CDS)
– 16-Bit Analog-to-Digital Conversion:
– Conversion Rate: 50 MHz
– No Missing Codes Ensured
• Input-Referred SNR: 80 dB at 12-dB Gain
• Programmable and Fast Black-Level Clamping
• Programmable Gain Amplifier (PGA):
0 dB to +51.15 dB
– Analog Gain: 0 dB to +18 dB
– Digital Gain: 0 dB to + 33.15 dB
– Additional CDS Gain: +3.5 dB
• Timing Generator:
– Fully Programmable V_RATE Timing with
Serial I/O
– Default Timing Supports Standard
Operation
– Flexible V_RATE Pin Assignment
– HD and VD Master or Slave Mode
– Flexible Draft or Pixel Summing Operation
– Supported Timing Range:
32767 Pixels × 8191 Lines
– Frame Memory Depth: 32
• RG and H_DRIVER:
– Programmable Drivability Control
– Two-Phase H_MODE
– Reset Gate Driver and HL Driver
• CCD Horizontal High-Speed Clock Phase
Control:
– Fine Step: 0.2 ns for 50 MHz
– DLL Range (H1, H2, HL, RG, MCKOUT, SHP,
SHD): Full Range of MCLK in 1/100th Steps
• Vertical CCD Driver:
– 16-Channel V_DRIVER with Sub-Driver
– Supports Motion and Still CCD Driving
– Three Level Drivers (V_TRANSFER) × 10
– Two Level Drivers (V_TRANSFER) × 2
– Two Level Small Drivers (V_TRANSFER) × 4
– Three Level Sub-Drivers (E_SHUTTER) × 1
– 6100 pF with 30 Ω
(Except two level small drivers)
• Flexible Voltage Operation:
– AVDD30: 2.7 V to 3.6 V
– IOVDD30: 1.8 V to 3.0 V
– RGVDD30: 2.7 V to 3.6 V
– HVDD30: 2.7 V to 3.6 V
– VL: –5.0 V to –8.0 V
– VM: GND
– VH: 11 V to 15 V
• Low Power Dissipation:
– Operation: 100 mW at 2.7 V (40 MHz)
– Standby Mode 1: 8 mW
– Standby Mode 2: 2 mW
• QFN-64 Package
DESCRIPTION
The VSP8133 is a complete, mixed-signal device for
charge-coupled device (CCD) signal processing with
a built-in CCD timing generator and an analog-to-
digital converter (ADC). The analog front-end (AFE)
CCD channel has correlated double sampling to
extract image information from the CCD output signal.
Signal paths have gains ranging from 0 dB to
+51.15 dB. The black-level clamping circuit enables
accurate black reference level and rapid black-level
recovery after gain changes. An input signal clamp is
also available. The system synchronizes the master
clock, horizontal driver (HD), and vertical driver (VD).
The VSP8133 supports all signal terminals that the
CCD requires. The RG driver and H_DRIVER
synchronize the ADC clock phase in order to achieve
ideal performance.
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
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All other trademarks are the property of their respective owners.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated