UCC5630 Datasheet, PDF (1/5 Pages) Texas Instruments – Low Voltage Differential LVD/SE SCSI 9 Line Terminator

UCC5630
Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator
FEATURES
• Auto Selection Multi-Mode Single
Ended or Low Voltage Differential
Termination
• 2.7V to 5.25V Operation
• Differential Failsafe Bias
• Thermal Packaging for Low Junction
Temperature and Better MTBF
• Master/Slave Inputs
• Supports Active Negation
• Standby (Disable Mode) 5µA
• 3pF Channel Capacitance
DESCRIPTION
The UCC5630 Multi-Mode Low Voltage Differential and Single Ended Ter-
minator is both a single ended terminator and a low voltage differential ter-
minator for the transition to the next generation SCSI Parallel Interface
(SPI-2). The low voltage differential is a requirement for the higher speeds
at a reasonable cost and is the only way to have adequate skew budgets.
The transceivers can be incorporated into the controller, unlike SCSI high
power differential (EIA485) which requires external transceivers. Low Volt-
age differential is specified for Fast-40 and Fast-80, but has the potential of
speeds up to Fast-320. The UCC5630 is SPI-2, SPI and Fast-20 compliant.
Consult SSOP-36 and LQFP-48 Package Diagram for exact dimensions.
The UCC5630 can not be used with SCSI high voltage differential (HVD)
EIA485. It will shut down when it sees high power differential to protect the
bus. The pinning for high power differential is not the same as LVD or sin-
gle ended and the bias voltage, current and power are also different for
EIA485 differential.
BLOCK DIAGRAM
SOURCE ONLY FROM TRMPWR AND THE ENABLED TERMINATORS
TRMPWR 36
MSTR/SLV 19
+V_DD
SOURCE 5 < 15mA
SINK 200µA MAXIMUM (NOISE LOAD)
REEF 1.3V
1.3V ± –0.1V
OPEN CIRCUIT ON POWER OFF
OR
OPEN CIRCUIT IN A DISABLED
TERMINATOR MODE
20
DIFFSENS
2.2 > 1.9V
20k
DIFFB
21
35 _HIPD
34 LVD
0.1µF
LOW
FREQUENCY
FILTER
50Hz – 60Hz
HS/GND 8
HS/GND 9
0.7 > 0.6V
REF 2.7V
SOURCE/SINK
REGULATOR
REF 1.25V
110
125 +50mV TO +62.5mV
HIGH IMPEDANCE
RECEIVER EVEN
WITH POWER OFF
33 SE
52
5 L1–
52
4 L1+
HS/GND 10
110
HS/GND 26
HS/GND 27
HS/GND 28
GND 18
DISCNCT 17
125 +50mV TO +62.5mV
SWITCHES UP ARE SINGLE
ENDED SWITCHES DOWN ARE
LOW VOLTAGE DIFFERENTIAL
52
52
SE GND
SWITCH
32 L9–
31 L9+
REG
1
MWP 36 PINOUT
4.7µF
Circuit Design Patented
01/99
UDG-98049