UCC5621MWP Datasheet, PDF (1/5 Pages) Texas Instruments – 27 - Line SCSI Terminator With Split Reverse Disconnect

UCC5621
27 - Line SCSI Terminator With Split Reverse Disconnect
FEATURES
• Complies with SCSI, SCSI-2, SCSI-3,
SPI and FAST-20 (Ultra) Standards
• 2.5pF Channel Capacitance During
Disconnect
• 100 A Supply Current in Disconnect
Mode
• 4V To 7V Operation
• 110 Termination
• Completely Meets SCSI Hot Plugging
• –900mA Sourcing Current for
Termination
• +500mA Sinking Current for Active
Negation
• Logic Command Disconnects all
Termination Lines
• Split Reverse Controls Lines 1 to 9
and 10 to 27 Separately
• Trimmed Impedance to 5%
• Current Limit and Thermal Shutdown
Protection
DESCRIPTION
UCC5621 provides 27 lines of active termination for a SCSI (Small Com-
puter Systems Interface) parallel bus. The SCSI standard recommends ac-
tive termination at both ends of the cable.
The UCC5621 is ideal for high performance 5V SCSI systems. During dis-
connect the supply current is typically only 100 A, which makes the IC at-
tractive for lower powered systems.
The UCC5621 features a split reverse disconnect allowing the user to con-
trol termination lines 10 to 27 with disconnect one, DISCNCT1, and control
terminiation lines 1 to 9 with disconnect two, DISCNCT2.
The UCC5621 is designed with a low channel capacitance of 2.5pF, which
eliminates effects on signal integrity from disconnected terminators at in-
terim points on the bus.
The power amplifier output stage allows the UCC5621 to source full termi-
nation current and sink active negation current when all termination lines
are actively negated.
The UCC5621, as with all Unitrode terminators, is completely hot plugga-
ble and appears as high impedance at the teminating channels with
VTRMPWR = 0V or open.
Internal circuit trimming is utilized, first to trim the 110 impedance, and
then most importantly, to trim the output current as close to the maximum
SCSI-3 specification as possible, which maximizes noise margin in FAST-
20 SCSI operation.
(continued)
BLOCK DIAGRAM
Circuit Design Patented
SLUS310A - OCTOBER 1998 - REVISED APRIL 2002
UDG-96111