TUSB6020_08 Datasheet, PDF (1/20 Pages) Texas Instruments – USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER

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TUSB6020
USB 2.0 HIGH-SPEED ON-THE-GO DUAL-ROLE CONTROLLER
SCPS170E – JANUARY 2007 – REVISED MARCH 2008
FEATURES
1
•23 USB On-the-Go (OTG) Controller Core
– Uses Mentor Graphics USB 2.0 OTG Core
– Dual-Role Controller Can Operate Either as
a Function Controller for a USB Peripheral
or as the Host/Peripheral in Point-to-Point
or Multipoint Communications With Other
USB Functions
– Compliant With the USB 2.0 Standard for
High-Speed (480-Mbps) Functions and With
OTG Supplement to USB 2.0 Specification
– Supports OTG Communications With One
or More High-, Full-, or Low-Speed Devices
– Supports Session Request Protocol (SRP)
and Host Negotiation Protocol (HNP)
– Supports Suspend-and-Resume Signaling
– Configurable for up to 4 Transmit
Endpoints or up to 4 Receive Endpoints
– Configurable FIFOs, Including the Option of
Dynamic FIFO Sizing
– 16k-Byte RAM for USB Endpoint FIFO
Shared by USB In/Out Endpoints
– Support for External Direct Memory Access
(DMA) to FIFOs
– Soft Connect/Disconnect Option
– Performs All Transaction Scheduling in
Hardware
• System Control Module
– Controls Clock and Reset Generation and
Distribution
– Controls and Observes Device Power
States
– Supports External Power Management
• Integrated USB 2.0 OTG PHY
– Fully Compliant with USB 2.0 Standard and
USB 2.0 Transceiver Macrocell Interface
(UTMI) Revision 1.05
– Optimized One-Port Operation at Low
Speed (1.5 Mbps), Full Speed (12 Mbps),
and High Speed (480 Mbps)
– Supports UTMI+3 Level 3 (Host and OTG
Devices, High/Full/Low Speed and
Preamble Packet)
– Protection Circuitry to Withstand Possible
VBUS Short
– Use 19.200-MHz or 24.000-MHz Reference
Clock Input as a Crystal or External Clock
Driver
– At-Speed Built-In Self Test (BIST) With
Internal Asynchronous Capability Through
Loopback
– On-Chip Integrated Accurate 45-Ω
High-Speed Termination, 1.5-kΩ Pullup, and
15-kΩ Pulldown Resistors
– On-Chip Phase-Locked Loop (PLL) to
Reduce Noise on High-Speed Clocks
– Active Power Consumption Less Than
100 mW
• VLYNQ 2.0 Interface to External Host
Controller
– High-Speed (150-MHz) Point-to-Point Serial
Interface for Direct Connection to Other
VLYNQ Interface
– Supports 4 Receive (RX) and 4 Transmit
(TX) Lines
– Memory-Mapped Master/Slave
– Hardware Flow Control Internal Loopback
Mode
– Multichannel DMA Controller
– Integrated List Processor Capable of
Parsing Communications Port
Programming Interface (CPPI)
3.0-Compliant Buffer Descriptors
• High-Performance 80-Pin
MicroStar BGA™/MicroStar Junior™
ZQE Package
• High-Performance 80-Pin PFC Package
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar BGA, MicroStar Junior are trademarks of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated