TSB83AA22C Datasheet, PDF (1/8 Pages) Texas Instruments – Phy and OHCI Link Device

TSB83AA22C
www.ti.com
SLLS851 – JUNE 2007
TSB83AA22C IEEE Std 1394b-2002 Phy and OHCI Link Device
FEATURES
• Fully Supports Provisions of IEEE Std
1394b-2002 Revision 1.33+ at 1-Gigabit
Signaling Rates
• Fully Supports Provisions of IEEE Std
1394a-2000 and IEEE Std 1394-1995 Standards
for High-Performance Serial Bus
• Fully Interoperable With Firewire™, i.LINK™,
and SB1394 Implementations of IEEE Std 1394
• Provides Two Fully Backward-Compatible,
IEEE Std 1394a-2000 Fully Compliant)
Bilingual IEEE Std 1394b-2002 Cable Ports at
up to 800 Megabits per Second (Mbps)
• Full IEEE Std 1394a-2000 Support Includes:
– Connection Debounce
– Arbitrated Short Reset
– Multispeed Concatenation
– Arbitration Acceleration
– Fly-By Concatenation
– Port Disable/Suspend/Resume
• Extended Resume Signaling for Compatibility
With Legacy DV Devices
• Power-Down Features to Conserve Energy in
Battery-Powered Applications
• Low-Power Sleep Mode
• Fully Compliant With Open Host Controller
Interface (OHCI) Requirements
• Cable Power Presence Monitoring
• Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
• Register Bits Give Software Control of
Contender Bit, Power-Class Bits, Link Active
Control Bit, and IEEE Std 1394a-2000 Features
• Interoperable With Other 1394 Physical Layers
(Phy) Using 1.8-V, 3.3-V, and 5-V Supplies
• Low-Jitter, External Crystal Oscillator
Provides Transmit and Receive Data at
100/200/400/800 Mbps and Link-Layer
Controller Clock at 49.152 MHz and
98.304 MHz
• Separate Bias (TPBIAS) for Each Port
• Software Device Reset (SWR)
• Fail-Safe Circuitry Senses Sudden Loss of
Power to the Device and Disables the Ports
Ensure That the TSB83AA22C Does Not Load
the TPBIAS of Any Connected Device and
Blocks any Leakage From the Port Back to
Power Plane
• IEEE Std 1394a-2000-Compliant
Common-Mode Noise Filter on Incoming Bias
Detect Circuit to Filter Out Crosstalk Noise
• Port Programmable to Force IEEE Std
1394a-2000 Mode to Allow Use of IEEE Std
1394a-2000 Connectors (IEEE Std 1394b-2002
Signaling Must Not Be Put Across IEEE Std
1394a-2000 Connectors or Cables)
• 3.3-V and 5-V PCI Signaling Environments
• Serial-Bus Data Rates of 100 Mbps, 200 Mbps,
400 Mbps, and 800 Mbps
• Physical Write Posting of up to Three
Outstanding Transactions
• Serial ROM or Boot ROM Interface Supports
2-Wire Serial EEPROM Devices
• 33-MHz/32-Bit PCI Interface
• Multifunction Terminal (MFUNC Terminal 1):
– PCI_CLKRUN Protocol per the PCI Mobile
Design Guide
– General-Purpose I/O
– CYCLEIN/CYCLEOUT for External Cycle
Timer Control for Customized
Synchronization
• PCI Burst Transfers and Deep FIFOs to
Tolerate Large Host Latency:
– Transmit FIFO—5K Asynchronous
– Transmit FIFO—2K Isochronous
– Receive FIFO—2K Asynchronous
– Receive FIFO—2K Isochronous
• D0, D1, D2, and D3 Power States and PME
Events per the PCI Bus Power Management
Interface Specification
• Programmable Asynchronous Transmit
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Firewire is a trademark of Apple Computer, Inc.
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated