TSB41LV06 Datasheet, PDF (1/39 Pages) Texas Instruments – IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER

TSB41LV06
IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
D Fully Supports Provisions of IEEE
1394–1995 Standard for High Performance
Serial Bus^† and the P1394a Supplement
(Draft 2.0)
D Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed concatenation, Arbitration
Acceleration, Fly-by Concatenation, Port
Disable/Suspend/Resume
D Provides Six P1394a Fully Compliant Cable
Ports at 100/200/400 Megabits per Second
(Mbits/s)
D Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
D Power-Down Features to Conserve Energy
in Battery Powered Applications include:
Automatic Device Power-Down during
Suspend, Device Power-Down Pin, Link
Interface Disable via LPS, and Inactive
Ports Powered Down
D Logic Performs System Initialization and
Arbitration Functions
D Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding
D Incoming Data Resynchronized to Local
Clock
SLLS289 – JANAURY1999
D Single 3.3 V Supply Operation
D Interface to Link Layer Controller Supports
Low Cost TI™ Bus-Holder Isolation and
Optional Annex J Electrical Isolation
D Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
D Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
D Interoperable with Link-Layer Controllers
Using 3.3-V and 5-V Supplies
D Interoperable with Other Physical Layers
(PHY) Using 3.3-V and 5-V Supplies
D Node Power Class Information Signaling
for System Power Management
D Cable Power Presence Monitoring
D Separate Cable Bias (TPBIAS) for Each Port
D Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Bit and P1394a Features
D Fully Interoperable with FIreWire™ and
i.LINK™ Implementation of IEEE Std 1394
D Low Cost, High Performance 100 Pin TQFP
(PZP) Thermally Enhanced Package
description
The TSB41LV06 provides the digital and analog transceiver functions needed to implement a six-port node in
a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV06 is designed to interface
with a Link Layer Controller (LLC), such as the TSB12LV22, TSB12LV21, TSB12LV31, TSB12LV41, or
TSB12LV01.
The TSB41LV06 requires only an external 24.576 MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates
the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock
signals used to control transmission of the outbound encoded Strobe and Data information. A 49.152 MHz clock
signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization
of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†Implements _{technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.}
i.LINK is a trademark of Sony Corporation
FireWire is a trademark of Apple Computers Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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