TSB21LV03 Datasheet, PDF (1/38 Pages) Texas Instruments – IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

TSB21LV03
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
D Supports Provisions of IEEE 1394-1995
Standard for High Performance Serial Bus^†
D Fully Interoperable with FireWire™
Implementation of IEEE 1394-1995
D Provides Three Fully Compliant Cable
Ports at 100/200 Megabits per Second
(Mbits/s)
D Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
D Device Power-Down Feature to Conserve
Energy in Battery-Powered Applications
D Inactive Ports Disabled to Save Power
D Logic Performs System Initialization and
Arbitration Functions
D Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding
D Incoming Data Resynchronized to Local
Clock
D Single 3.3-V Supply Operation
D Interface to Link-Layer Controller Supports
Optional Annex J Electrical Isolation and
TI™ Bus-Holder Isolation
SLLS230A – MARCH 1996 – REVISED DECEMBER 1996
D Data Interface to Link-Layer Controller
Provided Through 2/4 Parallel Lines at
50 Mbits/s
D 25-MHz Crystal Oscillator and PLL Provide
Transmit/Receive Data at 100/200 Mbits/s,
and Link-Layer Controller Clock at 50 MHz
D Interoperable with 1394 Link-Layer
Controllers Using 5-V Supplies
D Interoperable Across 1394 Cable with 1394
Physical Layers (Phy) Using 5-V Supplies
D Node Power-Class Information Signaling
for System Power Management
D Cable Power Presence Monitoring
D Separate Cable Bias and Driver Termination
Voltage Supply for Each Port
D Multiple Separate Package Terminals
Provided for Analog and Digital Supplies
and Grounds
D High Performance 64-Pin TQFP (PM)
Package
description
The TSB21LV03 provides the analog physical layer functions needed to implement a three-port node in a
cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB21LV03 is designed to interface
with a link-layer controller (LLC), such as the TSB12LV21, TSB12LV31, or TSB12C01A.
The TSB21LV03 requires either an external 24.576-MHz crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which generates the required 196.608-MHz reference signal. The
196.608-MHz reference signal is internally divided to provide the 49.152/98.304-MHz clock signals that control
transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also
supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the
received data. The power-down function, when enabled by taking the PD terminal high, stops operation of the
PLL and disables all circuitry except the cable-not-active signal circuitry.
The TSB21LV03 supports an optional isolation barrier between itself and its LLC. When ISO is tied high, the
link interface outputs behave normally. When ISO is tied low, internal differentiating logic is enabled, and the
outputs become short pulses, which can be coupled through a capacitor or transformer as described in the IEEE
1394-1995 Annex J.
† _{This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and INMOS, Limited.}
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Incorporated.
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1996, Texas Instruments Incorporated
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