TSB12LV26PZT Datasheet, PDF (1/5 Pages) Texas Instruments – OHCI-Lynx PCI-Based IEEE 1394 Host Controller

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OHCI-Lynx™ PCI-Based IEEE 1394 Host Controller
TSB12LV26
TSB12LV26I
SLLA214 – JUNE 2006
FEATURES
• 3.3-V and 5-V PCI bus signaling
• 3.3-V supply (core voltage is internally
regulated to 1.8 V)
• Serial bus data rates of 100M bits/s, 200M
bits/s, and 400M bits/s
• Physical write posting of up to three
outstanding transactions
• Serial ROM interface supports 2-wire devices
• External cycle timer control for customized
synchronization
• PCI burst transfers and deep FIFOs to
tolerate large host latency
• Two general-purpose I/Os
• Fabricated in advanced low-power CMOS
process
• Packaged in 100-terminal LQFP (PZT)
• PCI_CLKRUN protocol
DESCRIPTION
The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus
Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host
Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M
bits/s, 200M bits/s, and 400M bits/s serial bus data rates.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal
control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through
configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the
TSB12LV26 device is compliant with the PCI Bus Power Management Interface Specification, per the PC 99
Design Guide requirements. TSB12LV26 device supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at
132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are
provided to buffer 1394 data.
The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2
performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst
transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.
An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at
PCI clock rates up to 33 MHz.
NOTE:
This product is for high-volume PC applications only. For a complete datasheet or
more information contact [e-mail].
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OHCI-Lynx is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated