TSB12LV21A Datasheet, PDF (1/18 Pages) Texas Instruments – IEEE 1394-1995 BUS TO PCI BUS INTERFACE

TSB12LV21A
(PCILynx) IEEE 1394-1995 BUS TO PCI BUS INTERFACE
D Supports Provisions of IEEE 1394-1995
(1394) Standard for High-Performance
Serial Bus^†
D Performs the Function of a 1394 Cycle
Master
D Supports 1394 Transfer Rates of 100, 200
and 400 Mbit/s
D Provides Three Sizes of Programmable
FIFOs
D Provides PCI Bus Master Function for
Supporting DMA Operations
D Compliant With PCI Specification 2.1
SLLS273 – APRIL 1997
D Provides PCI Slave Function for Read/Write
Access of Internal Registers
D Supports the Plug-and-Play (PnP)
Specification
D Provides an 8-/16-bit Zoom Video (ZV) Port
for the Transferring of Video Data Directly
to an External Motion Video Memory Area
D Operates from a 3.3-V Power Supply While
Maintaining 5-V Tolerant Inputs
D High-Performance 176-Pin PQFP (PGF)
Package
description
The TSB12LV21A (PCILynx) provides a high-performance IEEE 1394-1995 interface with the capability to
transfer data between the 1394 phy-link interface, the PCI bus interface, and external devices connected to the
local bus interface. The 1394 phy-link interface provides the connection to the 1394 physical layer device and
is supported by the on-board link layer controller (LLC). The LLC provides the control for transmitting and
receiving 1394 packet data between the FIFO and phy-link interface at rates of 100 Mbit/s, 200 Mbit/s, and 400
Mbit/s. The link layer also provides the capability to receive status from the physical layer device and to access
the physical layer control and status registers by the application software.
An internal 1K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates
the need for external FIFOs. Separate FIFOs can be user configured to support 1394 receive, asynchronous
transmit, and isochronous transmit transfer operations.
The PCI interface supports 32-bit burst transfers up to 33 MHz and is capable of operating as both master and
target devices. Configuration registers can be loaded from an external serial EEPROM, allowing board and
system designers to assign their own unique identification codes. An autoboot mode allows data-moving
systems (such as docking stations) to be designed to operate on the PCI bus without the need for a host CPU.
The DMA controller uses packet control list (PCL) data structures to control the transfer of data and allow the
DMA to operate without host CPU intervention. These PCLs can reside in PCI memory or in memory that is
connected to the local bus port. The PCLs implement an instruction set that allows linking, conditional
branching, 1394 data transfer control, auxiliary support commands, and status reporting. Five DMA channels
are provided to accommodate programmable data types. PCLs can be chained together to form a channel
control program that can be developed to support each DMA channel. Data can be stored in either big endian
or little endian format eliminating the need for the host CPU to perform byte swapping. Data can be transferred
to either 4-byte aligned locations to provide the highest performance or to nonaligned locations to provide the
best memory use.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.}
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
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