TSB11LV01 Datasheet, PDF (1/21 Pages) Texas Instruments – 3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

TSB11LV01
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER
D Supports Provisions of IEEE 1394-1995
Standard for High Performance Serial Bus^†
D Fully Interoperable With FireWire™
Implementation of IEEE 1394-1995
D Provides A Single Fully-Compliant Cable
Port at 100 Megabits per Second (Mbits/s)
D Cable Port Monitors Line Conditions for
Active Connection to a Remote Node
D Inactive Port Disabled to Save Power
D Cable Inactivity Monitor Output and
Power-down Input Provided for Additional
Sleep-Mode Power Savings
D Internal Bandgap Reference Provided for
Setting Stable Operating Bias Conditions
D Logic Performs System Initialization and
Arbitration Functions
D Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding
D Incoming Data Resynchronized to Local
Clock
SLLS232B – MARCH 1996 – REVISED MAY 1997
D Data Interface to Link Layer Controller
(Link) Provided Through Two Parallel
Signal Lines at 50 Mbits/s
D 25-MHz Crystal Oscillator and PLL Provide
Transmit, Receive Data, and Link Layer
Controller Clocks at 50 MHz
D Digital I/Os are 5 V tolerant
D Node Power Class Information Signaling
for System Power Management
D Cable Power Presence Monitoring
D Cable Bias and Driver Termination Voltage
Supply
D Single 3-V Supply Operation
D Separate Multiple Package Terminals
Provided for Analog and Digital Supplies
and Grounds
D High Performance 48-Pin TQFP (PT)
Package
description
The TSB11LV01 provides the analog transceiver functions needed to implement a single port node in a cable
based IEEE 1394-1995 network. The cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status, for initialization and
arbitration, and for packet reception and transmission. The TSB11LV01 is designed to interface with a link layer
controller, such as the TSB12C01A.
The TSB11LV01 requires an external 24.576-MHz crystal, which drives an internal phase-locked loop (PLL)
generating the required 98.304-MHz reference signal. The 98.304-MHz reference signal is internally divided
to provide the 49.152-MHz ±100 ppm system clock signals that control transmission of the outbound encoded
strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link for
synchronization of the two chips and is used for resynchronization of the received data. The power-down
function, when enabled by asserting the PWRDN terminal high, stops operation of the PLL.
Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the
TSB11LV01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded,
and transmitted at 98.304-Mbits/s as the outbound data-strobe information stream. During transmit, the
encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information
is transmitted differentially on the TPA cable pair.
NOTE
In this document, phy is the physical layer and link is the link layer controller.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.}
FireWire is a trademark of Apple Computer, Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1