TRF3761 Datasheet, PDF (1/18 Pages) Texas Instruments – INTEGER-N PLL WITH INTEGRATED VCO

www.ti.com
INTEGER-N PLL WITH INTEGRATED VCO
TRF3761
SLWS181 – OCTOBER 2005
FEATURES
• Fully Integrated VCO
• Low Phase Noise: -138 dBc/Hz (at 600 kHz,
f_VCO of 1.9 GHz )
• Low Noise Floor: -160dBc/Hz at 10 MHz Offset
• Integer-N PLL
• Input Reference Frequency range: 10 104 MHz
• VCO Frequency Divided by 2-4 Output
• Output Buffer Enable Pin
• Programmable Charge Pump Current
• Hardware and Software Power Down
• 3-Wire Serial Interface
• Single Supply: 4.5 V 5.25 V Operation
• Silicon Germanium Technology
APPLICATIONS
• Wireless Infrastructure
– WCDMA
– CDMA
– GSM
RHA PACKAGE
(TOP VIEW)
PD_OUTBUF
CHIP_EN
CLOCK
DATA
STROBE
GND
GND
DVDD1
AVDD_PRES
GND
40 39 38 37 36 35 34 33 32 31
1
30
2
29
3
28
4
27
5
26
6
25
7
24
8
23
9
22
10
21
11 12 13 14 15 16 17 18 19 20
GND
AVDD_BIAS
RBIAS1
GND
VCTRL_IN
AVDD_VCO
AVDD_BUF
AVDD_CAPARRAY
GND
AVDD
DESCRIPTION
TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized for wireless
infrastructure applications. TRF3761 includes a low noise voltage controlled oscillator (VCO) and an integer-N
PLL.
TRF3761 integrates a divide-by-2 or 4 options for a more flexible output frequency range. It is controlled through
a 3-wire serial interface programming (SPI) interface. It can be powered down when it is not used by the SPI or
external pin.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2005, Texas Instruments Incorporated