TRF1216 Datasheet, PDF (1/2 Pages) Texas Instruments – 3.5-GHz, High Dynamic Range, Low-Noise Down-Converter

TRF1216
www.ti.com
SLWS172 – APRIL 2005
3.5-GHz, High Dynamic Range, Low-Noise Down-Converter
FEATURES
• Performs First Down-Conversion in 3.5-GHz
Radios (3300-3800 MHz)
• Integrated LNA/Mixer/ IF Amp/LO Buffer
• Provision for External Image Reject /
Band-Pass Filter
• Low Noise-Figure / High Linearity
• Switched 10-dB Attenuator for High-Level
Signals
• Frequency Range: 3.3 – 3.8 GHz
• 28 dB of Gain with 20 dB of Gain Control
(10-dB Switched)
• 2-dB Noise Figure, Typical Input
• Third Order Intercept of +5 dBm at 3.8 GHz
• LO Drive Level = 0 dBm, Typical
DESCRIPTION
The TRF1216 is the first of two integrated circuits
used in the receiver section of Texas Instruments’
3.5-GHz radio chipset. The TRF1216 down-converts
the 3.5-GHz input frequency to an intermediate fre-
quency in the range of 400 MHz to 500 MHz. The
device provides a differential output that passes
through a SAW filter before connecting to a second
down converter. For the best performance, Texas
Instruments TRF1212 should be used to perform both
the second down conversion and also provide the
Local Oscillator for the TRF1216.
The TRF1216 includes a LNA with switchable attenu-
ation, a balanced mixer, a variable gain IF amplifier
and a differential LO Buffer for improved perform-
ance. In order to provide exceptional image rejection
and extra jammer immunity, the TRF1216 offers a
signal path to an off-chip filter. Specifications are
provided assuming an in-band 2-dB insertion loss
filter. To maximize input dynamic range, a 10-dB
switchable attenuator is provided in the RF path as
well as 10dB of analog IF gain control. After the
image reject filter, an on-chip balun converts the
signal from single ended to differential in order to
provide better noise immunity at the mixer.
DEVICE INFORMATION
LPCC−20 PACKAGE
(TOP VIEW)
LNAO
VDDA
GND
GND
LNAI
20 19 18 17 16
1
15
2
14
3
13
4
12
5
11
6 7 8 9 10
RFAGC
IFOP
IFON
VDDIF
IFB
Figure 1. TRF1216 Pin Out
VDD1 VDD2 LNAO MXRI
LNAI
Dual Stage−
LNA
Mixer
BALUN
VDDIF
VGA
LO Buffer
RFATTN
GND
VDDLO
Figure 2. Block Diagram
IFB
IFOP
IFON
RFAGC
LOP
LON
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the forma-
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
Copyright © 2005, Texas Instruments Incorporated