TRF1112_07 Datasheet, PDF (1/25 Pages) Texas Instruments – Dual VCO/PLL Synthesizer With IF Down-Conversion

www.ti.com
TRF1112
TRF1212
SLWS175A – APRIL 2005 – REVISED DECEMBER 2005
Dual VCO/PLL Synthesizer With IF Down-Conversion
FEATURES
• Low Phase Noise
• High Dynamic Range Image-Reject
Downconverter
• Selectable IF Filters
• Internal or External AGC Control With Peak
Detector and Voltage Reference
• Analog Gain Control Range
• Direct Interface to A/D
• Dual VCO/PLL With On-Chip Resonator For
Double Down-Conversion Architecture
KEY SPECIFICATIONS
• S-Band LO Frequency Range:
– TRF1112: 1700 to 2400 MHz
– TRF1212: 2400 MHz to 3550 MHz
• UHF LO Frequency Range: 325 MHz to 460
MHz
• Phase Noise is 0.5 RMS Typ 100 Hz to 1 MHz
• Rx Noise Figure of 5 dB, Typ
• UHF LO Tuning Step Size of 125 kHz With 18
MHz Reference
• Typical Gain of 90 dB, Including 15-dB Loss
IF2 SAW Filter
• Input Third Order Intercept Point > 0 dBm
• Input 1-dB Compression Point > –10 dBm
• Gain Control Range of 90 dB Typ
DESCRIPTION
The TRF1112 / TRF1212 are UHF-VHF down
converters with integrated UHF and S-band
frequency synthesizers for radio applications in the
2GHz to 4GHz range. The device integrates an
image reject mixer, IF gain blocks, automatic gain
control (AGC), and two complete phase locked loop
(PLL) circuits including: VCOs, resonator circuit,
varactors, dividers, and phase detectors.
The TRF1112 / TRF1212 are designed to function as
part of Texas Instruments 2.5-GHz and 3.5-GHz
complete radio chipsets, respectively. In the chipset,
two chips function together to double-down convert
RF frequencies to an IF frequency that is suitable for
most baseband modem ADCs. The TRF1112 /
TRF1212 performs the second down conversion from
the first IF frequency (480 MHz typical) to a final IF
frequency (20-50 MHz). The radio chipset features
sufficient linearity, phase noise and dynamic range to
work in single carrier or multi-carrier, line-of-sight or
non-line-of-sight, IEEE standard 802.16, BWIF, or
proprietary systems. Due to the modular nature of the
chipset, it is ideal for use in systems that employ
transmit or receive diversity.
TRF1112 / TRF1212 PIN OUT
LPCC−48 PACKAGE
(TOP VIEW)
CP2O
1
LD1
2
LF1
3
EN
4
FRBP
5
VCCD1
6
FR
7
VCCD2
8
CLK
9
DATA
10
LF2
11
LD2
12
36
AGCO
35
IFBPB
34
IF1IP
33
IF1IN
32
VCCA
31
VCCB
30
VERR
29
VREF
28
VFB
27
VCCC
26
IF2AOP
25
IF2AON
BLOCK DIAGRAM
The detailed block diagram and the pin-out of the
ASIC are shown in Figure 1 and the Terminal
Functions table.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated