TPS56302 Datasheet, PDF (1/34 Pages) Texas Instruments – DUAL-OUTPUT LOW-INPUT-VOLTAGE DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 – MARCH 2000
D 2.8 V – 5.5 V Input Voltage Range
D Programmable Dual Output Controller
PWP PowerPAD™ PACKAGE
(TOP VIEW)
Supports Popular DSP, FPGA and
VID0
Microcontroller Core and I/O Voltages
VID1
– Switching Regulator Controls I/O Voltage _SLOWST
– Low Dropout Controller Regulates Core
VHYST
Voltage
VREFB
D Adjustable Slow-Start for Simultaneous
VSEN–RR
1
28
2
27
3
26
4
25
5
24
6 _Thermal 23
DROOP
OCP
IOUT
PWRGD
VSEN–LDO
NGATE–LDO
Powerup of Both Outputs
ANAGND
D Power Good Output Monitors Both Outputs
BIAS
D Fast Ripple Regulator Reduces Bulk
VLDODRV
CPC1
Capacitance for Lower System Costs
D ±1.5% Reference Voltage Tolerance
V_CC
CPC2
7
Pad
22
8
21
9
20
10
19
11
18
12
17
INHIBIT
IOUTLO
HISENSE
LOSENSE/LOHIB
HIGHDR
BOOT
D Efficiencies Greater Than 90%
VDRV
13
D Overvoltage, Undervoltage, and Adjustable ^DRVGND
14
16
BOOTLO
15
LDWDR
Overcurrent Protection
D Drives Logic Level N-Channel MOSFETs
AVAILABLE VID CODE RANGES
Through Entire Input Voltage Range
OUTPUTS
TPS56302
TPS56300
D Evaluation Module TPS56302EVM–163
VOUT–LDO
1.3 V TO 2.5 V
1.3 V TO 3.3 V
Available
VOUT–Switcher
1.3 V TO 3.3 V
1.3 V TO 2.5 V
description
NOTE: See Table 1 for actual VID codes.
The high-performance TPS56302 synchronous-buck regulator provides two supply voltages to power the core
and I/O of digital signal processors. The TPS56302 is identical to the TPS56300 except that the reference
voltages of the LDO and switching regulator have been reversed. The switching regulator, using hysteretic
control with droop compensation, supports high current and efficiency for the I/O and other peripheral
components. The LDO controller, suitable for powering the core voltage, drives an external N-channel power
MOSFET and functions as an LDO regulator and as a power distribution switch.
typical design
VI
(2.8 V – 5.5 V)
U1
TPS56302PWP
See Table 1
See Table 1
CPC1
CPC2
VCC PWRGD
NGATE–LDO
VREFB
VHYST
VSEN–LDO
DROOP
INHIBIT
OCP
IOUTLO
IOUT
HISENSE
SLOWST
VID0
HIGHDR
VSEN–RR
VID1
LOSENSE/LOHIB
BIAS
BOOT
VLDODRV
BOOTLO
VDRV
LOWDR
ANAGND
DRVGND
PwrPad
VCORE
VI/O ^DSP
Data
+
Data Bus
PERIPHERAL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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