TPS3836E18-EP Datasheet, PDF (1/15 Pages) Texas Instruments – NANOPOWER SUPERVISORY CIRCUITS

TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
www.ti.com.................................................................................................................................................... SGLS322D – MAY 2006 – REVISED NOVEMBER 2008
NANOPOWER SUPERVISORY CIRCUITS
FEATURES
1
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Supply Current of 220 nA (Typ)
• Precision Supply Voltage Supervision Range:
1.8 V, 2.5 V, 3 V, 3.3 V
• Power-On Reset Generator With Selectable
Delay Time of 10 ms or 200 ms
• Push/Pull RESET Output (TPS3836), RESET
Output (TPS3837), or
Open-Drain RESET Output (TPS3838)
• Manual Reset
• 5-Pin SOT-23 Package
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
• Controlled Baseline
• One Assembly/Test Site
• One Fabrication Site
• Available in Military (–55°C/125°C)
Temperature Range⁽¹⁾
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
TPS3836, TPS3838
DBV PACKAGE
(TOP VIEW)
CT ¹
5
V_DD
GND 2
MR ³
4
RESET
TPS3837
DBV PACKAGE
(TOP VIEW)
CT ¹
5
V_DD
GND 2
MR ³
4
RESET
APPLICATIONS
• Applications Using Automotive Low-Power
DSPs, Microcontrollers, or Microprocessors
• Battery-Powered Equipment
• Intelligent Instruments
• Wireless Communication Systems
• Automotive Systems
(1) Custom temperature ranges available
DESCRIPTION
The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing
supervision, primarily for digital signal processing (DSP) and processor-based systems.
During power on, RESET is asserted when the supply voltage V_DD becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors V_DD and keeps RESET output active as long as V_DD remains below the threshold
voltage (V_IT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time starts after V_DD has risen above V_IT.
When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to V_DD, the
delay time is typically 200 ms.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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