TPIC6C595DRG4 Datasheet, PDF (1/20 Pages) Texas Instruments – POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6C595
POWER LOGIC 8ĆBIT SHIFT REGISTER
D Low r_DS(on) . . . 7 Ω Typ
D Avalanche Energy . . . 30 mJ
D Eight Power DMOS Transistor Outputs of
100-mA Continuous Current
D 250-mA Current Limit Capability
D ESD Protection . . . 2500 V
D Output Clamp Voltage . . . 33 V
D Devices Are Cascadable
D Low Power Consumption
SLIS061C − JULY 1998 − REVISED APRIL 2005
D, N, OR PW PACKAGE
(TOP VIEW)
V_CC 1
SER IN 2
DRAIN0 3
DRAIN1 4
DRAIN2 5
DRAIN3 6
CLR 7
G8
16 GND
15 SRCK
14 DRAIN7
13 DRAIN6
12 DRAIN5
11 DRAIN4
10 RCK
9 SER OUT
description
The TPIC6C595 is a monolithic, medium-voltage,
logic symbol^†
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
G8
RCK ¹⁰
7
CLR
15
SRCK
EN3
C2
SRG8
R
C1
include relays, solenoids, and other low-current or
medium-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock
(RCK), respectively. The device transfers data out
the serial output (SER OUT) port on the rising
edge of SRCK. The storage register transfers data
to the output buffer when shift register clear (CLR)
SER IN ²
1D
3
2
DRAIN0
4
DRAIN1
5
DRAIN2
6
DRAIN3
11
DRAIN4
12
DRAIN5
13
DRAIN6
14
2
DRAIN7
9
SER OUT
is high. When CLR is low, the input shift register is
cleared. When output enable (G) is held high, all
data in the output buffers is held low and all drain
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984}
and IEC Publication 617-12.
outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When
data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor
outputs have sink-current capability. The SER OUT allows for cascading of the data from the shift register to
additional devices.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1998 − 2005, Texas Instruments Incorporated
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