TPIC6259DWG4 Datasheet, PDF (1/16 Pages) Texas Instruments – POWER LOGIC 8-BIT ADDRESSABLE LATCH

TPIC6259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995
• Low r_DS(on) . . . 1.3 Ω Typical
• Avalanche Energy . . . 75 mJ
DW OR N PACKAGE
(TOP VIEW)
• Eight Power DMOS Transistor Outputs of
250-mA Continuous Current
• 1.5-A Pulsed Current Per Output
• Output Clamp Voltage at 45 V
• Four Distinct Function Modes
• Low Power Consumption
PGND ₁
V_CC 2
S0 3
DRAIN0 4
DRAIN1 5
DRAIN2 6
20 ^PGND
19 CLR
18 D
17 DRAIN7
16 DRAIN6
15 DRAIN5
description
DRAIN3 7
S1 8
14 DRAIN4
13 G
This power logic 8-bit addressable latch controls
open-drain DMOS transistor outputs and is
LGND 9
PGND 10
12 S2
11 PGND
designed for general-purpose storage applica-
tions in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multi-
functional device capable of storing single-line
data in eight addressable latches with 3-to-8
INPUTS
CLR G D
H LH
HLL
FUNCTION TABLE
OUTPUT OF
ADDRESSED
DRAIN
L
H
EACH
OTHER
DRAIN
Qio
Qio
FUNCTION
Addressable
Latch
decoding or demultiplexing mode active-low
DMOS outputs.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
H HX
Qio
L LH
L
L LL
H
L HX
H
Qio
Memory
H
8-Line
H
Demultiplexer
H
Clear
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
LATCH SELECTION TABLE
terminal is written into the addressed latch. The
addressed DMOS transistor output inverts the
SELECT INPUTS
DRAIN
S2 S1 S0 ^ADDRESSED
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G should be held high (inactive) while the
LL L
0
LLH
1
LH L
2
LHH
3
HL L
4
HL H
5
HH L
6
HH H
7
address lines are changing. In the 3-to-8 decoding
or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are
high. In the clear mode, all outputs are high and unaffected by the address and data inputs.
Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,
and 20 are internally connected, and each pin must be externally connected to the power system ground in order
to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10,
11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the
logic and load circuits.
The TPIC6259 is characterized for operation over the operating case temperature range of – 40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1995, Texas Instruments Incorporated
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