TPIC5423L Datasheet, PDF (1/11 Pages) Texas Instruments – 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY

TPIC5423L
4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL
POWER DMOS ARRAY
SLIS045 – NOVEMBER 1994
• Low r_DS(on) . . . 0.32 Ω Typ
• Voltage Output . . . 60 V
• Input Protection Circuitry . . . 18 V
• Pulsed Current . . . 4 A Per Channel
• Extended ESD Capability . . . 4000 V
• Direct Logic-Level Interface
description
The TPIC5423L is a monolithic gate-protected
logic-level power DMOS array that consists of four
electrically isolated independent N-channel
enhancement-mode DMOS transistors. Each
transistor features integrated high-current zener
diodes (Z_CXa and Z_CXb) to prevent gate damage
in the event that an overstress condition occurs.
These zener diodes also provide up to 4000 V of
ESD protection when tested using the human-
body model of a 100-pF capacitor in series with a
1.5-kΩ resistor.
DW PACKAGE
(TOP VIEW)
DRAIN1 ₁
DRAIN1 ₂
GATE1 ₃
GND 4
SOURCE1 5
SOURCE1 6
SOURCE2 7
SOURCE2 8
GND 9
GATE2 10
DRAIN2 11
DRAIN2 12
24 ^DRAIN3
23 ^DRAIN3
22 ^GATE3
21 GND
20 SOURCE3
19 SOURCE3
18 SOURCE4
17 SOURCE4
16 GND
15 GATE4
14 DRAIN4
13 DRAIN4
The TPIC5423L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for
operation over the case temperature of – 40°C to 125°C.
schematic
1, 2
DRAIN1
GATE1 ³
Q1
ZC1b
5, 6 ^ZC1a
SOURCE1
DRAIN2 ^{11, 12}
D1 D3
Z1
Z3
Q3
ZC3b
ZC3a
10
GATE2
Q2
ZC2b
Z2 D2
D4
Z4
7, 8
SOURCE2
ZC2a
4, 9, 16, 21
GND
NOTE A: For correct operation, no terminal may be taken below GND.
Q4
ZC4b
ZC4a
23, 24
DRAIN3
22 _GATE3
19, 20
SOURCE3
13, 14
DRAIN4
15 _GATE4
17, 18
SOURCE4
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1994, Texas Instruments Incorporated
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