TPIC5401 Datasheet, PDF (1/12 Pages) Texas Instruments – H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY

D Low r_DS(on) . . . 0.3 Ω Typ
D High Voltage Output . . . 60 V
D Extended ESD Capability . . . 4000 V
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
D Pulsed Current . . . 10 A Per Channel
D Fast Commutation Speed
description
The TPIC5401 is a monolithic gate-protected power DMOS array that consists of four N-channel
enhancement-mode DMOS transistors, two of which are configured with a common source. Each transistor
features integrated high-current zener diodes (Z_CXa and Z_CXb) to prevent gate damage in the event that an
overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using
the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor.
The TPIC5401 is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body
surface-mount (DW) package and is characterized for operation over the case temperature range of – 40°C to
125°C.
NE PACKAGE
(TOP VIEW)
DW PACKAGE
(TOP VIEW)
DRAIN2 1
SOURCE2/GND 2
GATE2 3
GND 4
GND 5
GATE4 6
SOURCE4/GND 7
DRAIN4 8
16 SOURCE1
15 DRAIN1
14 GATE1
13 GND
12 GND
11 GATE3
10 DRAIN3
9 SOURCE3
GND ₁
SOURCE4/GND 2
GATE4 3
NC 4
DRAIN4 5
SOURCE3 6
DRAIN3 7
GATE3 8
NC 9
NC 10
20 ^SOURCE2/GND
19 GATE2
18 NC
17 NC
16 DRAIN2
15 SOURCE1
14 DRAIN1
13 GATE1
12 NC
11 NC
NC – No internal connection
schematic
DRAIN1
Q1
Z1
GATE1
ZC1b
ZC1a
SOURCE1
DRAIN2
Q2
GATE2
Z2
ZC2b
ZC2a
D1 D2
DRAIN3
Q3
Z3
GATE3
ZC3b
ZC3a
SOURCE3
DRAIN4
Q4
Z4
GATE4
ZC4b
ZC4a
GND, SOURCE2, SOURCE4
NOTE: For correct operation, no terminal pin may be taken below GND.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1994, Texas Instruments Incorporated
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