TPIC1533 Datasheet, PDF (1/17 Pages) Texas Instruments – QUAD AND HEX POWER DMOS ARRAY

TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
D Low r_DS(on):
0.1 Ω Typ (Full H-Bridge)
DW PACKAGE
(TOP VIEW)
0.22 Ω Typ (Triple Half H-Bridge)
D Pulsed Current:
OUTPUT3 ₁
GND ₂
24 ^V_DD3
23 ^GND
12 A Per Channel (Full H-Bridge)
6 A Per Channel (Triple Half H-Bridge)
D Matched Sense Transistors for Class A-B
GATE3B ₃
GATE2B 4
SENSE 5
22 ^GATE3A
21 GATE1B
20 GATE2C
Linear Operation
OUTPUT2 6
19 OUTPUT1
D Fast Commutation Speed
GATE4B 7
GATE2A 8
18 GATE4A
17 GATE1A
description
The TPIC1533 is a monolithic power DMOS array
that consists of ten electrically isolated N-channel
GATE5B 9
V_DD2 10
OUTPUT4 11
SOURCE 12
16 GATE5A
15 V_DD1
14 V_DD3
13 OUTPUT5
enhancement-mode power DMOS transistors, four
of which are configured as a full H-bridge and six as a triple half H-bridge. The lower stage of the full H-bridge
is provided with an integrated sense-FET to allow biasing of the bridge in class A-B operation.
The TPIC1533 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of – 40°C to 125°C.
schematic
VDD1
15
VDD2
10
VDD3
14, 24
Q1A
17
GATE1A
Q2A
8
GATE2A
Q3A
22
GATE3A
Q4A
18
GATE4A
Q5A
16
GATE5A
19
OUTPUT1
D1
D2
6
1
OUTPUT2 OUTPUT3
Q1B
21
GATE1B
Q2B
4
GATE2B
Q3B
3
GATE3B
11
OUTPUT4
Q4B
7
GATE4B
13
OUTPUT5
Q5B
9
GATE5B
SENSE ⁵
20
GATE2C
Q2C
6V
D4
D5
D6
D3
12
SOURCE
2, 23
GND
NOTES: A. Terminals 2 and 23 must be externally connected.
B. Terminals 14 and 24 must be externally connected.
C. No output may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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