TPA5052 Datasheet, PDF (1/10 Pages) Texas Instruments – STEREO DIGITAL AUDIO LIP-SYNC DELAY

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TPA5052
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
STEREO DIGITAL AUDIO LIP-SYNC DELAY
FEATURES
• Digital Audio Format: 16-24-bit I²S
• Single Serial Input Port
• Delay Time: 170 ms/ch at fs = 48 kHz
• Delay Resolution: 256 samples
• Delay Memory Cleared on Power-Up or After
Delay Changes
– Eliminates Erroneous Data From Being
Output
• 3.3 V Operation With 5 V Tolerant I/O
• Supports Audio Bit Clock Rates of 32 to 64 fs
with fs = 32 kHz–192 kHz
• No External Crystal or Oscillator Required
– All Internal Clocks Generated From the
Audio Clock
• Surface Mount 4mm × 4mm, 16-pin QFN
Package
APPLICATIONS
• High Definition TV Lip-Sync Delay
• Flat Panel TV Lip-Sync Delay
• Home Theater Rear-Channel Effects
• Wireless Speaker Front-Channel
Synchronization
• Camcorders
DESCRIPTION
The TPA5052 accepts a single serial audio input,
buffers the data for a selectable period of time, and
outputs the delayed audio data on a single serial
output. In systems with complex video processing
algorithms, one device allows delay of up to
170 ms/ch (fs = 48 kHz) to synchronize the audio
stream to the video stream. If more delay is needed,
the devices can be connected in series.
Audio Processor
SIMPLIFIED APPLICATION DIAGRAM
SCLK
TAS3103A
or
ATSC
Processor
BCLK
LRCLK
DATA
TPA5052
3.3 V
BCLK
LRCLK
DATA
DATA_OUT
Digital Amplifier
TAS5504A
+TAS5122
SCLK
BCLK
LRCLK
DATA
5
Fixed Delay
Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated