TMS470R1VF689 Datasheet, PDF (1/70 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLERS

TMS470R1VF689, TMS470R1VF688
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS001I – FEBRUARY 2002 – REVISED AUGUST 2005
O High-Performance Static CMOS Technology
O TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (48-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
O Integrated Memory (VF689 only)
– 384K-Byte Program Flash
– Three Banks With 18 Contiguous Sectors
– 16K-Byte Static RAM (SRAM)
O Integrated Memory (VF688 only)
– 256K-Byte Program Flash
– Two Banks With 14 Contiguous Sectors
– 12K-Byte Static RAM (SRAM)
O Operating Features
– Core Supply Voltage (V_CC): 1.71 V - 2.05 V
– I/O Supply Voltage (V_CCIO): 3.0 V - 3.6 V
– Low-Power Modes: STANDBY and HALT
– Industrial/Automotive Temperature Ranges
O 470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
O Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
O Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
O Ten Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Two Serial Communication Interfaces (SCIs)
– 2²⁴ Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– Two Standard CAN Controllers (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Class II Serial Interface (C2SIb)
– Normal 10.4 Kbps and 4X Mode 41.6 Kbps
– Three Inter-Integrated Circuit (I2C) Modules
– Multi-Master and Slave Interfaces
– Up to 400 Kbps (Fast Mode)
– 7- and 10-Bit Address Capability
O High-End Timer (HET)
– 12 Programmable I/O Channels:
– 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 64-Instruction Capacity
O External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
O 12-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 32-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
O Flexible Interrupt Handling
O Expansion Bus Module (EBM) (PGE only)
– Supports 8- and 16-Bit Expansion Bus Mem-
ory Interface Mappings
– 40 I/O Expansion Bus Pins
O 55 Dedicated General-Purpose I/O (GIO) Pins
and 39 Additional Peripheral I/Os (PGE Suffix))
O 14 Dedicated GIO Pins and 39 Additional Pe-
ripheral I/Os (PZ Suffix)
O Eight External Interrupts
O Compatible ROM Device (Planned)
O On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1⁽¹⁾ (JTAG) Test-Access
Port
O 144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
O 100-Pin Plastic Low-Profile Quad Flatpack
(PZ Suffix)
O Development System Support Tools Available
– Code Composer Studio™ Integrated
Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
1 The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
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