TMS470R1VF48C Datasheet, PDF (1/67 Pages) Texas Instruments – 16/32-BIT RISC FLASH MICROCONTROLLERS

TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
O High-Performance Static CMOS Technology
O TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 60-MHz System Clock (Pipeline Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
O Integrated Memory (VF48C only)
– 1M-Byte Program Flash
–Two Banks With 16 Contiguous Sectors
– 64K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
O Integrated Memory (VF48B only)
– 768K-Byte Program Flash
– Two Banks With 12 Contiguous Sectors
– 48K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
O Operating Features
– Low-Power Modes: STANDBY and HALT
– Industrial/Automotive Temperature Ranges
O 470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
O Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
O Frequency-Modulated Zero-Pin Phase-Locked
Loop (FM_ZPLL)-Based Clock Module With
Prescaler
– Multiply-by-8 Internal FM_ZPLL Option
– ZPLL Bypass Mode
O Twelve Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Three Serial Communication Interfaces
(SCIs)
– 2²⁴ Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
– Two High-End CAN Controllers (HECC)
– 32-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Five Inter-Integrated Circuit (I2C) Modules
– Multi-Master and Slave Interfaces
– Up to 400 Kbps (Fast Mode)
– 7- and 10-Bit Address Capability
O High-End Timer Lite (HET)
– 12 Programmable I/O Channels:
– 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 64-Instruction Capacity
O External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
O 12-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
O Flexible Interrupt Handling
O Expansion Bus Module (EBM)
– Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
– 42 I/O Expansion Bus Pins
O 46 Dedicated General-Purpose I/O (GIO) Pins
and 47 Additional Peripheral I/Os
O Sixteen External Interrupts
O Compatible ROM Device (Planned)
O On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1⁽¹⁾ (JTAG) Test-Access
Port
O 144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
O Development System Support Tools Available
– Code Composer Studio™ Integrated Devel-
opment Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
1 The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
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