TMS320C44 Datasheet, PDF (1/42 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

D Highest Performance Floating-Point Digital
Signal Processor (DSP)
– TMS320C44-60:
33-ns Instruction Cycle Time,
330 MOPS, 60 MFLOPS,
30 MIPS, 336M Bytes / s
– TMS320C44-50:
40-ns Instruction Cycle Time
D Four Communication Ports
D Six-Channel Direct Memory Address (DMA)
Coprocessor
D Single-Cycle Conversion to and From
IEEE-754 Floating-Point Format
D Single Cycle, 1/x, 1/√x
D Source-Code Compatible With ’320C3x and
’320C4x
D Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
D Twelve 40-Bit Registers, Eight Auxiliary
Registers, 14 Control Registers,
and Two Timers
D IEEE-1149.1^† (JTAG) Boundary-Scan
Compatible
D Two Identical External Data and Address
Buses Supporting Shared Memory
Systems and High Data-Rate,
Single-Cycle Transfers
– High Port-Data Rate of 120M Bytes / s
(TMS320C44-60) (Each Bus)
– 128M-Byte Program / Data / Peripheral
Address Space
– Memory-Access Request for Fast,
Intelligent Bus Arbitration
– Separate Address-Bus, Data-Bus, and
Control-Enable Pins
– Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
D 304-Pin Plastic Quad Flatpack
(PDB Suffix)
D Fabricated Using 0.72-µm Enhanced
Performance Implanted CMOS (EPIC™)
Technology by Texas Instruments (TI™)
D Separate Internal Program-, Data-, and
DMA-Coprocessor Buses for Support of
Massive Concurrent I / O of Program and
Data, Thereby Maximizing Sustained CPU
Performance
TMS320C44
DIGITAL SIGNAL PROCESSOR
304
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SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
PDB PACKAGE
( TOP VIEW )‡
229
228
76
77
153
152
‡ _{See Pin Assignments table and Pin Functions table for location}
and description of all pins.
D IDLE2 Clock-Stop Power-Down Mode
D Communication-Port-Direction Pin
D On-Chip Program Cache and
Dual-Access/ Single-Cycle RAM for
Increased Memory-Access Performance
– 512-Byte Instruction Cache
– 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
– ROM-Based Boot Loader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories or One of the Communication
Ports
D Software-Communication-Port Reset
D NMI With Bus-Grant Feature
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture}
EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
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