TMS29LF040 Datasheet, PDF (1/38 Pages) Texas Instruments – 524288 BY 8-BIT FLASH MEMORIES

D Single Power Supply
3.3 V ± 0.3 V – TMS29LF040
2.7 V to 3.6 V – TMS29VF040
5 V ± 10% – See TMS29F040 Data sheet
(Literature Number SMJS820)
D Organization . . . 524288 By 8 Bits
D Eight Equal Sectors of 64K Bytes
– Any Combination of Sectors Can Be
Erased
– Any Combination of Sectors Can Be
Marked as Read-Only
D Compatible With JEDEC Electrically
Erasable Programmable Read-Only
Memory (EEPROM) Command Set
D Fully Automated On-Chip Erase and
Byte-Program Operations
D 100000 Program / Erase Cycles
D Erase-Suspend/ Erase-Resume Operation
D Compatible With JEDEC Byte-Wide Pinouts
D Low-Current Consumption
– Active Read . . . 20 mA Typical
– Active Program / Erase . . . 30 mA Typical
D All Inputs/Outputs CMOS-Compatible Only
TMS29LF040, TMS29VF040
524288 BY 8-BIT
FLASH MEMORIES
SMJS825D – SEPTEMBER 1995 – REVISED JUNE 1998
FM PACKAGE
( TOP VIEW )
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
A14
A13
A8
A9
A11
G
A10
E
DQ7
PIN NOMENCLATURE
A[0:18]
DQ[0:7]
E
G
VCC
VSS
W
Address Inputs
Inputs (programming) / Outputs
Chip Enable
Output Enable
Power Supply
Ground
Write Enable
description
The TMS29LF040 and TMS29VF040 are 524 288 by 8-bit (4 194 304-bit), low-voltage, single-supply,
programmable read-only memories that can be erased electrically and reprogrammed. These devices are
organized as eight independent 64K-byte sectors and are offered with access times between 80 ns and
150 ns.
An on-chip state machine controls the program and erase operations. The embedded-byte program and
sector/ chip-erase functions are fully automatic. The command set is compatible with that of JEDEC 4M-bit
EEPROMs. A suspend / resume feature allows access to unaltered memory sectors during a sector-erase
operation. Data protection of any sector combination is accomplished using a hardware sector-protection
feature.
Device operations are selected by writing JEDEC-standard commands into the command register using
standard microprocessor-write timings. The command register acts as input to an internal state machine that
interprets the commands, controls the erase and programming operations, and outputs the status of the device,
the data stored in the device, and the device algorithm-selection code. On initial power-up operation, the device
defaults to the read mode.
The TMS29xF040 is offered in a 32-pin 8 x 14 mm thin small-outline package (DBW suffix), a 32-pin
8 x 20 mm thin small-outline package (DD suffix), and a 32-pin plastic leaded chip carrier (FM suffix) using
1.27 mm (50-mil) lead pitch.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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