TM893CBK32 Datasheet, PDF (1/9 Pages) Texas Instruments – DYNAMIC RAM MODULE

D Organization
TM893CBK32 . . . 8 388 608 × 32 Bit
D Single 5-V Power Supply (±10% Tolerance)
D 72-Pin, Leadless Single In-Line Memory
Module ( SIMM) for Use With Sockets
D TM893CBK32 – Utilizes Sixteen 16-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead ( SOJ) Packages
D Long Refresh Period
32 ms (2048 Cycles)
D All Inputs, Outputs, Clocks Fully TTL
Compatible
D 3-State Output
D Common CAS Control for Eight Common
Data-In and Data-Out Lines in Four Blocks
D Enhanced Page-Mode Operation With
CAS-Before-RAS ( CBR), RAS-Only, and
Hidden Refresh
TM893CBK32, TM893CBK32S
8388608 BY 32-BIT
DYNAMIC RAM MODULE
SMMS652A – FEBRUARY 1995 – REVISED JUNE 1995
D Presence Detect
D Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME TIME OR
tRAC
tAA
tCAC WRITE
CYCLE
(MAX)
(MAX) (MAX) (MIN)
’893CBK32-60 60 ns
30 ns 15 ns 110 ns
’893CBK32-70 70 ns
35 ns 18 ns 130 ns
’893CBK32-80 80 ns
40 ns
D Low Power Dissipation
20 ns 150 ns
D Operating Free-Air-Temperature Range
0°C to 70°C
D Gold-Tabbed Versions Available:^†
TM893CBK32
D Tin-Lead (Solder) Tabbed Versions
Available:
TM893CBK32S
description
The TM893CBK32 is a 32-megabyte, dynamic random-access memory organized as four times 8 388 608 × 8
bits in a 72-pin, leadless single in-line memory module ( SIMM). The SIMM is composed of 16 TMS417400DJ,
4 194 304 × 4-bit dynamic RAMs, each in 24 / 26-lead plastic small-outline J-lead ( SOJ) packages mounted on
a substrate with decoupling capacitors. The TMS417400DJ is described in the TMS417400 data sheet. The
TM893CBK32 SIMM is available in the double-sided BK leadless module for use with sockets.
operation
The TM893CBK32 operates as sixteen TMS417400DJs connected as shown in the functional block diagram
and Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention on D and Q.
refresh
The refresh period is extended to 32 ms, and during this period each of the 2048 rows must be strobed with RAS
to retain data. To conserve power, CAS can remain high during the refresh sequence.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full V_CC level is achieved. These eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
† _{Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.}
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
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