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SNJ54ALS873B Datasheet, PDF (1/9 Pages) Texas Instruments – DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A
DUAL 4-BIT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS036D – APRIL 1982 – REVISED AUGUST 1995
• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Bus-Structured Pinout
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
description
These dual 4-bit D-type latches feature 3-state
outputs designed specifically for bus driving.
These devices are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The dual 4-bit latches are transparent D-type
latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs in true
form, according to the function table. When LE is
low, the outputs are latched. When the clear (CLR)
input goes low, the Q outputs go low
independently of LE. The outputs are in the
high-impedance state when the output-enable
(OE) input is at a high logic level.
The SN54ALS873B and SN54AS873A are
characterized for operation over the full military
temperature range of – 55°C to 125°C. The
SN74ALS873B and SN74AS873A are
characterized for operation from 0°C to 70°C.
SN54ALS873B, SN54AS873A . . . JT PACKAGE
SN74ALS873B, SN74AS873A . . . DW OR NT PACKAGE
(TOP VIEW)
1CLR 1
1OE 2
1D1 3
1D2 4
1D3 5
1D4 6
2D1 7
2D2 8
2D3 9
2D4 10
2OE 11
GND 12
24 VCC
23 1LE
22 1Q1
21 1Q2
20 1Q3
19 1Q4
18 2Q1
17 2Q2
16 2Q3
15 2Q4
14 2LE
13 2CLR
SN54ALS873B, SN54AS873A . . . FK PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
1D2 5
25 1Q2
1D3 6
24 1Q3
1D4 7
23 1Q4
NC 8
22 NC
2D1 9
21 2Q1
2D2 10
20 2Q2
2D3 11
19 2Q3
12 13 14 15 16 17 18
NC – No internal connection
FUNCTION TABLE
(each latch)
INPUTS
OE CLR LE
OUTPUT
D
Q
L
L
X
X
L
L
H
H
H
H
L
H
H
L
L
L
H
L
X
Q0
H
X
X
X
Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
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