SNJ54ABT16373A Datasheet, PDF (1/7 Pages) Texas Instruments – 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54ABT16373A, SN74ABT16373A
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS160C – DECEMBER 1992 – REVISED MAY 1997
D Members of the Texas Instruments
Widebus™ Family
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 5 V, T_A = 25°C
D High-Impedance State During Power Up
and Power Down
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16373A are 16-bit transparent D-type
latches with 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
SN54ABT16373A . . . WD PACKAGE
SN74ABT16373A . . . DGG OR DL PACKAGE
(TOP VIEW)
1OE ₁
1Q1 ₂
1Q2 ₃
GND ₄
1Q3 ₅
1Q4 ₆
V_{CC 7}
1Q5 ₈
1Q6 ₉
GND ₁₀
1Q7 ₁₁
1Q8 ₁₂
2Q1 ₁₃
2Q2 ₁₄
GND ₁₅
2Q3 ₁₆
2Q4 ₁₇
V_{CC 18}
2Q5 ₁₉
2Q6 ₂₀
GND ₂₁
2Q7 ₂₂
2Q8 23
2OE 24
48 ^1LE
47 ^1D1
46 ^1D2
45 ^GND
44 ^1D3
43 ^1D4
42 ^V_CC
41 ^1D5
40 ^1D6
39 ^GND
38 ^1D7
37 ^1D8
36 ^2D1
35 ^2D2
34 ^GND
33 ^2D3
32 ^2D4
31 ^V_CC
30 ^2D5
29 ^2D6
28 ^GND
27 ^2D7
26 2D8
25 2LE
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16373A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16373A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
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