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SN75LVDS84A_07 Datasheet, PDF (1/16 Pages) Texas Instruments – FLATLINK TRANSMITTER
SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
D 21:3 Data Channel Compression at up to
196 Million Bytes per Second Throughput
D Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With Very Low EMI
D 21 Data Channels Plus Clock In
Low-Voltage TTL Inputs and 3 Data
Channels Plus Clock Out Low-Voltage
Differential Signaling (LVDS) Outputs
D Operates From a Single 3.3-V Supply and
89 mW (Typ)
D Ultralow-Power 3.3-V CMOS Version of the
SN75LVDS84. Power Consumption About
One Third of the ’LVDS84
D Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20 Mil Terminal
Pitch
D Consumes Less Than 0.54 mW When
Disabled
D Wide Phase-Lock Input Frequency Range:
31 MHz to 75 MHz
D No External Components Required for PLL
D Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D SSC Tracking Capability of 3% Center
Spread at 50-kHz Modulation Frequency
D Improved Replacement for SN75LVDS84
and NSC’s DS90CF363A 3-V Device
D Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
SLLS354E – MAY 1999 – REVISED JANUARY 2001
DGG PACKAGE
(TOP VIEW)
D4 1
VCC 2
D5 3
D6 4
GND 5
D7 6
D8 7
VCC 8
D9 9
D10 10
GND 11
D11 12
D12 13
NC 14
D13 15
D14 16
GND 17
D15 18
D16 19
D17 20
VCC 21
D18 22
D19 23
GND 24
48 D3
47 D2
46 GND
45 D1
44 D0
43 NC
42 LVDSGND
41 Y0M
40 Y0P
39 Y1M
38 Y1P
37 LVDSVCC
36 LVDSGND
35 Y2M
34 Y2P
33 CLKOUTM
32 CLKOUTP
31 LVDSGND
30 PLLGND
29 PLLVCC
28 PLLGND
27 SHTDN
26 CLKIN
25 D20
NC – Not Connected
description
The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift
registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair
conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.
When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.
The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The
three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2001, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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