SN75LVDS84 Datasheet, PDF (1/14 Pages) Texas Instruments – FLATLINKE TRANSMITTERS

SN75LVDS84, SN75LVDS85
FLATLINK™ TRANSMITTERS
D 21:3 Data Channel Compression at up to
163 Million Bytes per Second Throughput
D Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With Very Low EMI
D 21 Data Channels Plus Clock In
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential
D Operates From a Single 3.3-V Supply and
250 mW (Typ)
D 5-V Tolerant Data Inputs
D ESD Protection Exceeds 6 kV
D SN75LVDS84 Has Falling Clock-Edge
Triggered Inputs, SN75LVDS85 Has Rising
Clock-Edge-Triggered Inputs
D Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
D Consumes Less Than 1 mW When Disabled
D Wide Phase-Lock Input Frequency Range:
31 MHz to 68 MHz
D No External Components Required for PLL
D Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D Improved Replacement for the DS90C561
SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999
DGG PACKAGE
(TOP VIEW)
D4 ₁
V_{CC 2}
D5 ₃
D6 4
GND 5
D7 6
D8 7
V_CC 8
D9 9
D10 10
GND 11
D11 12
D12 13
NC 14
D13 15
D14 16
GND 17
D15 18
D16 19
D17 20
V_CC 21
D18 22
D19 ²³
GND ²⁴
48 ^D3
47 ^D2
46 ^GND
45 D1
44 D0
43 NC
42 LVDSGND
41 Y0M
40 Y0P
39 Y1M
38 Y1P
37 LVDSV_CC
36 LVDSGND
35 Y2M
34 Y2P
33 CLKOUTM
32 CLKOUTP
31 LVDSGND
30 PLLGND
29 PLLV_CC
28 PLLGND
27 SHTDN
26 _CLKIN
25 _D20
description
NC – Not Connected
The SN75LVDS84 and SN75LVDS85 FlatLink transmitters each contain three 7-bit parallel-load serial-out shift
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be
synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as
the SN75LVDS82 or SN75LVDS86.
When transmitting, data bits D0 – D20 are each loaded into registers of the SN75LVDS84 upon the falling edge
and into the registers of the SN75LVDS85 on the rising edge of the input clock signal (CLKIN). The frequency
of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The
three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.
AVAILABLE OPTIONS†
LATCHING CLOCK EDGE
FALLING
RISING
SN75LVDS84DGG
SN75LVDS84DGGR
SN75LVDS85DGG
SN75LVDS85DGGR
† _{The R suffix indicates taped and reeled packaging.}
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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