SN75LVDS82 Datasheet, PDF (1/15 Pages) Texas Instruments – FLATLINKE RECEIVER

SN75LVDS82
FLATLINK™ RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MAY 1999
D 4:28 Data Channel Expansion at up to 227.5
Million Bytes per Second (Mbytes/s)
DGG PACKAGE
(TOP VIEW)
Throughput
D Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D 4 Data Channels and Clock Low-Voltage
Differential Channels In and 28 Data and
Clock Low-Voltage TTL Channels Out
D Operates From a Single 3.3-V Supply With
250 mW Typ
D 5-V Tolerant SHTDN Input
D22 ₁
D23 ₂
D24 ₃
GND 4
D25 5
D26 6
D27 7
LVDSGND 8
A0M 9
A0P 10
56 ^V_CC
55 ^D21
54 ^D20
53 D19
52 GND
51 D18
50 D17
49 D16
48 V_CC
47 D15
D Falling Clock-Edge-Triggered Outputs
D Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
D Consumes Less Than 1 mW When Disabled
D Wide Phase-Lock Input Frequency
Range . . . 31 MHz to 68 MHz
D No External Components Required for PLL
A1M 11
A1P 12
LVDSV_CC 13
LVDSGND 14
A2M 15
A2P 16
CLKINM 17
CLKINP 18
46 D14
45 D13
44 GND
43 D12
42 D11
41 D10
40 V_CC
39 D9
D Inputs Meet or Exceed the Requirements of
A3M 19 38 D8
the ANSI EIA/TIA-644 Standard
A3P 20 37 D7
D Improved Replacement for the National
DS90C582
LVDSGND 21
PLLGND 22
PLLV_CC 23
36 GND
35 D6
34 D5
description
PLLGND ²⁴
SHTDN ²⁵
33 D4
32 _D3
The SN75LVDS82 FlatLink™ receiver contains
four serial-in 7-bit parallel-out shift registers, a 7×
clock synthesizer, and five low-voltage differential
signaling (LVDS) line receivers in a single
CLKOUT ²⁶
D0 ²⁷
GND ²⁸
31 _VCC
30 _D2
29 _D1
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the
SN75LVDS81, over five balanced-pair conductors and expansion to 28 bits of single-ended low-voltage TTL
(LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84
or SN75LVDS85 for 21-bit transfers.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×)
the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate.
A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).
The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low-level on SHTDN clears all internal registers to a low level.
The SN75LVDS82 is characterized for operation over ambient air temperatures of 0_C to 70_C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a registered trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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